LM93 datasheet(32/95 Pages) TI1

32 / 95 page

LM93

SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

www.ti.com

Channel #

Input

Typical Assignment

Temp Zone 1

Remote Diode 1 Temp Reading

Temp Zone 2

Remote Diode 2 Temp Reading

Temp Zone 3

Internal Temperature Reading

AIN1

+12V1

AIN2

+12V2

AIN3

+12V3

AIN4

FSB_Vtt

AIN5

3GIO/PXH/MCH_Core

AIN6

ICH_Core

AIN7

CPU_1Vccp

AIN8

CPU2_Vccp

AIN9

3.3V

AIN10

+5V

AIN11

SCSI_Core

AIN12

Mem_Core

AIN13

Mem_Vtt

AIN14

GBIT_Core

AIN15

−12V

AIN16

3.3V SB VDD Supply Rail

3.16.6 ERROR STATUS REGISTERS

The LM93 contains several error status registers for the BMC side, and duplicated error status registers

for the Host side. These registers are used to reflect the state of all the possible error conditions that the

LM93 monitors.

The BMC/Host Error Status registers hold a set bit until the event is cleared by software, even if the

condition causing the error event goes away.

To clear a bit in the Error Status registers, a ‘1’ has to be written to the specific bit that is required to be

cleared. If the event that caused the error is no longer active then the bit is cleared.

Clearing a bit in a BMC Error Status register does not clear the corresponding bit in the Host Error Status

3.16.6.1 ASF Mode

In order for the LM93 part to act as a legacy sensor (6.1.2 of ASF spec DSP0114 rev 2) and to easily bolt

up to the SMBus of an ASF capable NIC chip, the treatment of the Error Status registers needs to change.

The LM93 can be placed into ASF mode by setting the appropriate bit in the LM93 Status/Control register.

Once this bit is set, the BMC Error Status registers become read-to-clear. Writing a ‘1’ to clear a particular

bit is also allowed in ASF mode. The Host Error Status registers are not effected by ASF mode.

3.16.7 MASKING, ERROR STATUS AND ALERT

Masking is always applied to bits in the HOST and BMC Error Status registers. If an event is masked, the

corresponding error bit in the HOST or BMC Error Status registers is prevented from ever being set. As a

result, this prevents the event from ever causing ALERT to be asserted. Masking an event does not clear

its associated Error Status bit if it is currently set.

Voltage errors are masked by writing a high voltage limit value of FFh. This is the default high limit for all

voltages.

Functional Description

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LM93 Datasheet(PDF) 32 Page - Texas Instruments

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