LM93 datasheet(70/95 Pages) TI1

70 / 95 page

LM93

SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

www.ti.com

Note that changing this value while PROCHOT measurements are running may cause the monitoring

circuit to produce a erroneous value. To avoid alerts and invalid B_Px_PROCHOT or B_Px_PROCHOT

Error Status values, only change this value while the chip is programmed for S3 or S4/5.

3.17.8.13 Register C8h

PWM1 Control 1

Read/

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

Name

Value

PWM1

VRD1

PH2

PH1

ZN4

ZN3

ZN2

ZN1

C8h

R/W

VRD2

0Fh

Control 1

Bit

Name

R/W

Description

ZN1

R/W

If set, PWM1 will be bound to temperature zone 1.

ZN2

R/W

If set, PWM1 will be bound to temperature zone 2.

ZNE

R/W

If set, PWM1 will be bound to temperature zone 3.

ZN4

R/W

If set, PWM1 will be bound to temperature zone 4.

PH1

R/W

If set, PWM1 will be bound to P1_PROCHOT.

PH2

R/W

If set, PWM1 will be bound to P2_PROCHOT.

VRD1

R/W

If set, PWM1 will be bound to VRD1_HOT1.

VRD2

R/W

If set, PWM1 will be bound to VRD1_HOT2.

This register can bind PWM1 to several different control sources. The temperature zones control the PWM

duty cycle using the table lookup function. The Px_PROCHOT and VRDx_HOT inputs control the PWM

using the ramp up/ramp down functions. If multiple control sources are bound to PWM1, the largest duty

cycle being requested will be used.

3.17.8.14 Register C9h

PWM1 Control 2

Read/

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

Name

Value

PWM1

EPPL

INV

OVR

C9h

R/W

OVR_DC

00h

Control 2

Bit

Name

R/W

Description

OVR

R/W

When set, enables manual duty cycle override for PWM1.

INV

R/W

Invert PWM1 output. When 0, 100% duty cycle corresponds to the PWM output

continuously HIGH. When 1, 100% duty cycle corresponds to the PWM output

continuously LOW.

EPPL

R/W

Enable PROCHOT PWM1 lock. When set, this bit causes bound PROCHOT events

on PWM1 to trigger PPL (bit [3]). When cleared, PPL never gets set.

PPL

R/W

PROCHOT PWM1 lock. When set, this bit indicates that PWM1 is currently being

held at 100% because a bound PROCHOT event occurred while EPPL (bit [2]) was

set. This bit is cleared by writing a zero. Clearing this bit allows the fans to return to

normal operation. This bit is not locked by the LOCK bit in the LM93 Configuration

7:4

OVR_DC

R/W

This field sets the duty cycle that will be used by PWM1 whenever manual override

mode is active. This field accepts 16 possible values that are mapped to duty cycles

according the table in the FAN CONTROL section. Whenever this register is read, it

returns the duty cycle that is currently being used by PWM1 regardless of whether

override mode is active or not. The value read may not match the last value written

if another control source is requesting a greater duty cycle. This field always returns

0h when the PWM1 spin up cycle is active.

3.17.8.15 Register CAh

PWM1 Control 3

Read/

Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Address

Write

Name

Value

PWM1

RES

SU_DC

CAh

R/W

SU_DUR

00h

Control 3

Functional Description

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