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LM93 Datasheet(PDF) 76 Page - Texas Instruments |
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LM93 Datasheet(HTML) 76 Page - Texas Instruments |
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76 / 95 page  LM93 SNAS210E – DECEMBER 2003 – REVISED MARCH 2013 www.ti.com Lock Bit Name R/W Description X 1 LOCK R/W Setting this bit locks all registers and register bits that are indicated as lockable. Lockable registers have an “x” in the Lock column of their description. This register is locked once it is set. This bit can only be cleared by an external device asserting RESET. 2 GMSK R/W Global Mask When this bit is set by software, all error events are masked. Setting this bit does not effect any other mask registers or value registers. 3 ALERT_EN R/W When this bit is set, the ALERT output is enabled. If this bit is cleared, the ALERT output is disabled. 4 P1P2_ R/W In some configurations it may be required to have both processors throttling PROCHOT at the same rate. When this bit is set, the LM93 connects P1_PROCHOT to P2_PROCHOT. If P1_PROCHOT and P2_PROCHOT are already shorted by some other means, this bit should NOT be set. Doing so would cause both PROCHOT signals to be stuck low until this bit is cleared. 6:5 RES R/W Reserved 7 READY R The LM93 sets this bit automatically after valid data has been collected for all temperatures and voltages. Software should not use any temperature or voltage values until this bit has been set. 3.17.9 SLEEP STATE CONTROL AND MASK REGISTERS 3.17.9.1 Register E4h Sleep State Control Register Read/ Register Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address Write Name Value Sleep SB E4h R State RES 07h Control Bit Name R/W Description 1:0 SB R/W Sleep State Control. Setting this field tells the LM93 which sleep state the system is in. Several error events are masked depending on the state of this field. 7:2 RES R Reserved SPACER SB Description 00 Sleep state = S0 Do not mask errors. 01 Sleep state = S1 Mask errors according to S1 mask registers and standard S1 masking. 10 Sleep state = S3 Mask errors according to S3 mask registers and standard S3 masking. 11 Sleep state = S4/5 Mask errors according to S4/5 mask registers and standard S4/5 masking. This mode is activated automatically if the RESET input is asserted. 3.17.9.2 Register E5h S1 GPI Mask Register Read/ Register Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address Write Name Value S1 GPI GPI7_S1 GPI6_S1 GPI5_S1 GPI4_S1 GPI3_S1 GPI2_S1 GPI1_S1 GPI0_S1 E5h R/W FFh Mask _MSK _MSK _MSK _MSK _MSK _MSK _MSK _MSK 76 Functional Description Copyright © 2003–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: LM93 |
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