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LM93 Datasheet(PDF) 63 Page - Texas Instruments |
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LM93 Datasheet(HTML) 63 Page - Texas Instruments |
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63 / 95 page ![]() LM93 www.ti.com SNAS210E – DECEMBER 2003 – REVISED MARCH 2013 SPACER UPPER_OFFSET1 or Upper Offset UPPER_OFFSET2 0h 12.5 mV 1h 25 mV 2h 37.5 mV 3h 50 mV ~ ~ ~ ~ Dh 175 mV Eh 187.5 mV Fh 200 mV 3.17.7.6 Register B4–BBh Fan Tach Limit Registers Register Read/ Register Default Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Address Write Name Value Fan Tach RES B4h R/W 1 TLIMIT1[5:0] FCh Limit LSB Fan Tach 1 B5h R/W TLIMIT1[13:6] FFh Limit MSB Fan Tach B6h R/W 2 TLIMIT2[5:0] RES FCh Limit LSB Fan Tach 2 B7h R/W TLIMIT2[13:6] FFh Limit MSB Fan Tach B8h R/W 3 TLIMIT3[5:0] RES FCh Limit LSB Fan Tach 3 B9h R/W TLIMIT1[13:6] FFh Limit MSB Fan Tach BAh R/W 4 TLIMIT4[5:0] RES FCh Limit LSB Fan Tach 4 BBh R/W TLIMIT4[13:6] FFh Limit MSB If a tachometer reading exceeds its limit (as defined by these registers) the corresponding bit is set in the Host and BMC Error Status registers. The fan tachometer readings can be associated with a particular PWM output, but the tach errors are not automatically masked when a PWM is at 0% or set to level that causes the fan RPM to be below the limit purposely. In order to prevent false errors, care needs to be taken to make sure that the Fan Tach Limits are properly set. Errors are never generated for a fan if its limit is set to 3FFFh. Copyright © 2003–2013, Texas Instruments Incorporated Functional Description 63 Submit Documentation Feedback Product Folder Links: LM93 |
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