LM93 datasheet(15/95 Pages) TI1

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LM93

www.ti.com

SNAS210E – DECEMBER 2003 – REVISED MARCH 2013

Value Register

VIN

Δ from −12V

106

-10.9597

8.6688

107

-10.9351

8.8745

108

-10.9104

9.0803

109

-10.8857

9.2861

110

-10.8610

9.4919

111

-10.8363

9.6976

112

-10.8116

9.9034

113

-10.7869

10.1092

3.7

DYNAMIC Vccp MONITORING USING VID

The AD_IN7 (CPU1 Vccp) and AD_IN8 (CPU2 Vccp) inputs are dynamically monitored using the P1_VIDx

and P2_VIDx inputs to determine the limits. The dynamic comparisons operate independently of the static

comparisons which use the statically programmed limits.

According to the VRM/VRD 10 specification when a VID signal is ramping to a new value, it steps by one

LSB at a time, and one step occurs every 5 µs. In worse case, up to 20 steps may occur at once over 100

µs. The Vccp voltage from the VRD has to settle to the new value within 50 µs of the last VID change. The

LM93 expects that the VID changes will not occur more frequently than every 5 µs.

The VID signal can be changed by the processor under program control, by internal thermal events or by

external control, like force PROCHOT.

The reference voltages selected by each value of the 6 bit VID can be found in the VRM/VRD 10 spec.

Transient VID values caused by line-to-line skew are ignored by the LM93. See the VRM/VRD 10 spec for

the worst case line-to-line skew.

The LM93 averages the VID values over a sampling window to determine the average voltage that the

VID input was indicating during the sampling window. At the completion of a voltage conversion cycle the

LM93 performs limit comparisons based on average VID values and not instantaneous values. The upper

limit is determined by adding the upper limit offset to the average voltage indicated by VID. The lower limit

is determined by subtracting the lower limit offset from average voltage indicated by VID. If the AD_IN7 (or

AD_IN8) voltage falls outside the upper and lower limits, an error event is generated. Dynamic and static

comparisons are performed once every 100 ms. The averaging time interval is 1.5 ms.

If at any time during the Vccp sampling window, the VID code indicates that the VRD should turn off its

output, the dynamic Vccp checking is disabled for that sample.

The comparison accuracy is ±25 mV, therefore the comparison limits must be set to include this error.

Since the Vccp voltage may be in the process of settling to a new value (due to a VID change), this

settling should be taken into account when setting the upper and lower limit offsets.

The LM93 has a limitation on the upper limit voltage for dynamic Vccp checking. The upper limit cannot

exceed 1.5875V. If the sum of the voltage indicated by VID and the upper offset voltage exceed 1.5875,

the upper limit checking is disabled.

3.8

VREF OUTPUT

VREF is a fixed voltage to be used by an external VRD or as a voltage reference input for the BMC A/D

inputs. VREF is 2.5V ±1%. There is internal current limit protection for the VREF output in case it gets

shorted to supply or ground accidentally.

Functional Description

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