BT8376EPF datasheet(113/323 Pages) CONEXANT

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Bt8370/8375/8376

2.0 Circuit Description

Fully Integrated T1/E1 Framer and Line Interface

2.10 Microprocessor Interface

N8370DSE

Conexant

2-85

2.10.4 Device Reset

The Bt8370/8375/8376 contains three reset methods: internal power-on reset

(POR), hardware reset which uses the RST* pin, and software reset which uses

the RESET bit in register CR0 [addr 001]. All three methods result in device

outputs placed in a high-impedance state and configuration registers set to default

values as shown in Table 3-1, Address Map. In all reset methods, both REFCLK

and MCLK (internal or external) must be present during the reset process for

proper operation. MCLK (internal or external) performs the actual register

initialization. Therefore, if the CLKMD pin is connected high to enable external

MCLK, the external MCLK must be applied during reset, and if the CLKMD pin

is low during reset, the internal clock (33 MHz) is used.

After hardware reset, software reset, or internal power-on reset, the

microprocessor must initialize Bt8370/8375/8376 control registers and buffer

memory registers to the desired state.

2.10.4.1 Power-On

Reset (POR)

An internal POR process is initiated during power-up. When VDD has reached

approximately 3 V, the internal reset process begins and continues for 2048

REFCLK cycles (approximately 205 µs) if REFCLK is applied. If REFCLK is

not present, the Bt8370/8375/8376 remains in the reset state and does not

terminate until detecting 2048 REFCLK cycles have been detected. The RESET

bit in register CR0 [addr 001] can be monitored to determine when POR is

complete. MCLK (internal or external) must be present during the POR

concurrent with REFCLK to allow register initialization.

The LOOP register [addr 014] is not reset during power-on reset or internal

reset so the device may occasionally power-on in a loopback state. If this occurs,

several other registers (e.g., several IER registers) may not properly reset to their

default values. To avoid this, after power-on or hardware reset, write the Loop

Control register [CR0; addr 001]. After this procedure, all default registers have

their default values. XOE needs to be disabled during the power-on reset period

and re-enabled after configuring the part. The device must not be in Framer

Loopback State when the software reset is written.

2.10.4.2 Hardware

Reset

Hardware Reset is initiated by bringing the RST* pin active (low) for a minimum

of 4 µs. If CLKMD is high (using external MCLK), external MCLK must be

present while RST* is low to allow register initialization. After RST* is

deactivated, the internal reset process continues for 5 µs, and register access must

be avoided. The RESET bit in register CR0 [addr 001] can be monitored to

determine when the reset process is complete.

2.10.4.3 Software Reset

Software Reset is initiated by writing the RESET bit [register CR0; addr 001] to

0, delaying at least 6 µs, then writing RESET to 1. Once initiated, the reset

process continues for 15 µs maximum and register access must be avoided. The

RESET bit can be monitored to determine when the reset process has completed.

As with the other reset methods, both REFCLK and MCLK (internal or external)

must be present during the reset process.

BT8376EPF Datasheet(PDF) 113 Page - Synaptics Incorporated.

BT8376EPF Datasheet(HTML) 113 Page - Synaptics Incorporated.

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