BT8376EPF datasheet(112/323 Pages) CONEXANT

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2.0 Circuit Description

Bt8370/8375/8376

2.10 Microprocessor Interface

Fully Integrated T1/E1 Framer and Line Interface

2-84

Conexant

N8370DSE

2.10.1 Address/Data Bus

In Non-multiplexed Address mode, A[8:0] provides the address for register

access; in Multiplexed Address mode, A[8] and AD[7:0] provide the address. In

both modes, the data bytes flow over the shared bidirectional, byte-wide bus,

AD[7:0].

2.10.2 Bus Control Signals

Four signals control the operation of the interface port: AS*, CS*, RD*, and

R/W*. An additional pin, MOTO*, selects whether the interface signals are of a

Motorola or Intel flavor.

When MOTO* is low, indicating a Motorola-style interface, CS*, AS*, R/W*,

and DS* signals are expected. When MOTO* is high, indicating an Intel-style

interface, CS*, ALE, RD*, and WR* signals are expected.

When MOTO* is high, the address lines are multiplexed with the data. This

pin is usually tied high for Intel devices, and low for Motorola devices. SYNCMD

puts the interface into the Synchronous Processor Interface mode. Motorola

68000 processors typically have SYNCMD tied high if MCLK is connected to the

MPU clock source, while Intel 8051 processors have SYNCMD tied low (see

Table 2-24).

2.10.3 Interrupt Requests

The INTR* output is an active low, open-drain type output which allows the

interrupt request line from multiple devices to connect to a common

microprocessor interrupt request line. All the Bt8370/8375/8376 interrupts are

requested on this pin. However, each interrupt source can be individually enabled

or disabled.

Interrupts are associated with three types of microprocessor interface

registers:

•

Interrupt Enable register—a 1 in a given bit of IER[7:0] enables the

corresponding interrupt, a 0 (initial condition) disables it.

•

Interrupt Status register [ISR; 7:0]—events are latched into these registers

whether the corresponding interrupt enable bit is set or not. The processor

must read the ISR registers to clear all latched bits.

•

Interrupt Request register [IRR; addr 003]—reading this register along

with the corresponding ISR register, the microprocessor can determine the

cause of an interrupt. Active interrupts are indicated by bits that are high.

Inactive interrupts are indicated by bits that are low. Reading from IRR

clears the entire register; writing has no effect.

Table 2-24. Microprocessor Interface Operating Modes

MOTO*

SYNCMD

CLKMD

Description

Asynchronous Motorola, internal clock

Synchronous Motorola, external clock

Asynchronous Intel, internal clock

Synchronous Intel, external clock

BT8376EPF Datasheet(PDF) 112 Page - Synaptics Incorporated.

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