BT8376EPF datasheet(129/323 Pages) CONEXANT

129 / 323 page

Bt8370/8375/8376

3.0 Registers

Fully Integrated T1/E1 Framer and Line Interface

3.2 Global Control and Status Registers

N8370DSE

Conexant

3-11

002—Jitter Attenuator Configuration (JAT_CR)

The processor writes JAT_CR register at power-up, activating the JAUTO and JCENTER bits to initialize the

jitter attenuator elastic store. The processor can maximize jitter tolerance by repeating JCENTER after

recovering from an error [CKERR; addr 006] on the JAT input clock reference. JAT elastic store automatically

recenters upon detection of an elastic store limit error [JERR; addr 006].

JEN

Jitter Attenuator Enable—JCLK and CLADO are locked to the timing reference selected. The

reference frequency can operate at T1 or E1 line rates, or at any rate supported by the clock

rate adapter. See RSCALE[2:0] [addr 092] for selecting the timing reference frequency.

JFREE

Free-Running JCLK and CLADO—Disables both CLADI and JAT phase detectors in the

clock rate adapter, which forces the Numerical Controlled Oscillator (NCO) to free-run based

on the 10 MHz REFCKI input clock accuracy. When JFREE is active, JEN and JDIR select

jitter attenuator direction.

0 = normal (closed loop) CLAD/JAT operation

1 = free run (open loop) NCO operation

JDIR

Select JAT Direction—Applicable only when the jitter attenuator is enabled (see JEN

description). JAT elastic store is placed in either the receive or transmit direction, and JCLK is

placed on RCKO or TCKO pin according to JDIR selection.

0 = JAT in TX direction, JCLK output on TCKO

1 = JAT in RX direction, JCLK output on RCKO

JEN

JFREE

JDIR

JAUTO

JCENTER

JSIZE[2]

JSIZE[1]

JSIZE[0]

CEN

JEN

JFREE

JDIR

CLADO/JCLK Reference

REFCKI—Free running 10 MHz clock

REFCKI—Free running 10 MHz clock with transmit JAT

REFCKI—Free running 10 MHz clock with receive JAT

TXCLK—TCKI or ACKI per [AISCLK; addr 068]

RXCLK—RPLL or RCKI per [RDIGI; addr 020]

CLADI—System clock, bypass JAT elastic store

CLADI—System clock with transmit JAT

CLADI—System clock with receive JAT

NOTE:

JCLK always operates at T1 or E1 line rate selected by [T1/E1N; addr 001].

BT8376EPF Datasheet(PDF) 129 Page - Synaptics Incorporated.

BT8376EPF Datasheet(HTML) 129 Page - Synaptics Incorporated.

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