BT8376EPF datasheet(192/323 Pages) CONEXANT

192 / 323 page

Bt8370/8375/8376

3.12 Transmitter Registers

Fully Integrated T1/E1 Framer and Line Interface

3-74

Conexant

N8370DSE

073—Transmit Error Insert (TERROR)

Transmit error insertion capabilities are provided for system diagnostic, production test, and test equipment

applications. Writing a 1 to any TERROR bit injects a single occurrence of the respective error on

TPOSO/TNEGO and XTIP/XRING outputs. Writing a 0 has no effect. Multiple transmit errors can be

generated simultaneously. Injected errors also affect data sent during either a Framer or Analog Loopback

[FLOOP or ALOOP; addr 014].

TSERR

Inject CAS Multiframe (MAS) Error—Injects a single MAS pattern error. TSERR performs a

logical inversion of the first MAS bit transmitted.

0 = no effect

1 = inject MAS error

TMERR

Inject Multiframe Error—Injects a single Fs (T1) or MFAS bit (E1) error. TMERR performs a

logical inversion of the next multiframe bit transmitted. The processor can pace writing to

TMERR to control which MFAS bit is errored.

0 = no effect

1 = inject multiframe error

TBERR

Inject PRBS Test Pattern Error—Injects a single PRBS error by logically inverting the next

PRBS generator output bit. The processor can pace writing to TBERR to create the desired bit

error ratio (up to 5E-3 if TBERR asserted 1/192 bits at every frame interrupt).

0 = no effect

1 = inject PRBS error

BSLIP/TCOFA

Inject Transmit COFA—Forces a 1-bit shift in the location of transmit frame alignment by

deleting (or inserting) one bit position from the transmit frame. During E1 modes, BSLIP

determines in which direction the bit slip will occur. In T1 modes, only one bit deletion is

provided. Note that TCOFA alters the extraction rate of data from the transmit slip buffer; thus,

repeated TCOFAs eventually cause a controlled frame slip where one frame of data is repeated

(T1/BSLIP = 0) or where one frame of data is deleted (BSLIP = 1).

TCERR

Inject CRC Error—Injects a single CRC6 (T1) or CRC4 (E1) bit error. TCERR logically invert

the next CRC bit transmitted. The processor can pace writing to TCERR to control which CRC

bit is errored.

0 = no effect

1 = inject CRC error

TFERR

Inject Frame Bit Error—Injects a single Ft, FPS, or FAS bit error, depending on the selected

transmit framer mode. TFERR logically invert the next frame bit transmitted. The processor

can pace writing to TFERR, to control which frame bit is errored.

0 = no effect

1 = inject frame error

TSERR

TMERR

TBERR

BSLIP

TCOFA

TCERR

TFERR

TVERR

TCOFA

T1/E1N

BSLIP

Transmit COFA

No effect

Inhibit output of TS0 bit 1 for one frame

Insert 1 prior to FAS pattern for one frame

Inhibit output of F-bit for one frame

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