SC1100 datasheet(189/348 Pages) NSC

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Core Logic Module (Continued)

Index AEh

CPU Suspend Command Register (WO)

Reset Value: 00h

7:0

Software CPU Suspend Command. If bit 0 in the Clock Stop Control register is set low (F0 Index BCh[0] = 0), a write to

this register causes an internal SUSP#/SUSPA# handshake with the GX1 module, placing the GX1 module in a low-power

state. The actual data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the GX1 module halt con-

dition.

If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the internal SUSP_3V signal is

asserted after the SUSP#/SUSPA# halt. Upon a Resume event, the PLL delay programmed in the F0 Index BCh[7:4] is

invoked, allowing the clock chip and GX1 module PLL to stabilize before deasserting SUSP#.

Index AFh

Suspend Notebook Command Register (WO)

Reset Value: 00h

7:0

Software CPU Stop Clock Suspend. A write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing

the GX1 module in a low-power state. Following this handshake, the SUSP_3V signal is asserted. The SUSP_3V signal is

intended to be used to stop all system clocks.

Upon a Resume event, the internal SUSP_3V signal is deasserted. After a slight delay, the Core Logic module deasserts

the SUSP# signal. Once the clocks are stable, the GX1 module deasserts SUSPA# and system operation resumes.

Index B0h-B3h

Reserved

Reset Value: 00h

Index B4h

Floppy Port 3F2h Shadow Register (RO)

Reset Value: xxh

7:0

Floppy Port 3F2h Shadow. Last written value of I/O Port 3F2h. Required for support of FDC power On/Off and 0V Sus-

pend/Resume coherency.

This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of

when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.

Index B5h

Floppy Port 3F7h Shadow Register (RO)

Reset Value: xxh

7:0

Floppy Port 3F7h Shadow. Last written value of I/O Port 3F7h. Required for support of FDC power On/Off and 0V Sus-

pend/Resume coherency.

This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of

when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.

Index B6h

Floppy Port 372h Shadow Register (RO)

Reset Value: xxh

7:0

Floppy Port 372h Shadow. Last written value of I/O Port 372h. Required for support of FDC power On/Off and 0V Sus-

pend/Resume coherency.

This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of

when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.

Index B7h

Floppy Port 377h Shadow Register (RO)

Reset Value: xxh

7:0

Floppy Port 377h Shadow. Last written value of I/O Port 377h. Required for support of FDC power On/Off and 0V Sus-

pend/Resume coherency.

This register is a copy of an I/O register which cannot safely be directly read. The value in this register is not deterministic of

when the register is being read. It is provided here to assist in a Suspend-to-Disk operation.

Index B8h

DMA Shadow Register (RO)

Reset Value: xxh

7:0

DMA Shadow. This 8-bit port sequences through the following list of shadowed DMA Controller registers. At power on, a

pointer starts at the first register in the list and continuing through the other registers in subsequent reads according to the

read sequence. A write to this register resets the read sequence to the first register. Each shadow register in the sequence

contains the last data written to that location.

The read sequence for this register is:

1. DMA Channel 0 Mode Register

2. DMA Channel 1 Mode Register

3. DMA Channel 2 Mode Register

4. DMA Channel 3 Mode Register

5. DMA Channel 4 Mode Register

6. DMA Channel 5 Mode Register

7. DMA Channel 6 Mode Register

8. DMA Channel 7 Mode Register

9. DMA Channel Mask Register (bit 0 is channel 0 mask, etc.)

10. DMA Busy Register (bit 0 or 1 means a DMA occurred within last 1 msec, all other bits are 0)

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

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SC1100 Datasheet(PDF) 189 Page - National Semiconductor (TI)

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