SC1100 datasheet(206/348 Pages) NSC

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Revision 1.1

Core Logic Module (Continued)

SMI Source is Serial IRQ. Indicates whether or not an SMI was generated by an SERIRQ.

0: No.

1: Yes.

Write 1 to clear.

To enable SMI generation, set bit 9 of this register to 1.

This is the second level of status reporting. The top level status is reported in F1BAR0+I/O Offset 02h[3].

Writing a 1 to this bit also clears the top level status bit as long as bit 5 of this register is cleared.

LPC Error Status. Indicates whether or not an SMI was generated by an error that occurred on LPC.

0: No.

1: Yes.

Write 1 to clear.

To enable SMI generation, set bit 8 of this register to 1.

This is the second level of status reporting. The top level status is reported in F1BAR0+I/O Offset 02h[3].

Writing a 1 to this bit also clears the top level status bit as long as bit 6 of this register is cleared.

LPC Multiple Errors Status. Indicates whether or not multiple errors have occurred on LPC.

0: No.

1: Yes.

Write 1 to clear.

LPC Timeout Error Status. Indicates whether or not an error was generated by a timeout on LPC.

0: No.

1: Yes.

Write 1 to clear.

LPC Error Write Status. Indicates whether or not an error was generated during a write operation on LPC.

0: No.

1: Yes.

Write 1 to clear.

LPC Error DMA Status. Indicates whether or not an error was generated during a DMA operation on LPC.

0: No.

1: Yes.

Write 1 to clear.

LPC Error Memory Status. Indicates whether or not an error was generated during a memory operation on LPC.

0: No.

1: Yes.

Write 1 to clear.

Offset 20h-23h

LPC_ERR_ADD — LPC Error Address Register (RO)

Reset Value: 00000000h

31:0

LPC Error Address.

Table 5-31. F0BAR1+I/O Offset xxh: LPC Interface Configuration Registers (Continued)

Bit

Description

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