SC1100 datasheet(210/348 Pages) NSC

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Revision 1.1

Core Logic Module (Continued)

SMI Source is Software Generated. (Read to Clear) Indicates whether or not an SMI was caused by software.

0: No.

1: Yes.

SMI on an A20M# Toggle. (Read to Clear) Indicates whether or not an SMI was caused by an access to either Port 92h or

the keyboard command which initiates an A20M# SMI.

0: No.

1: Yes.

This method of controlling the internal A20M# in the GX1 module is used instead of a pin.

To enable SMI generation, set F0 Index 53h[0] to 1.

6:4

Reserved. Reads as 0.

SMI Source is LPC. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by the LPC interface.

0: No.

1: Yes.

The next level (second level) of SMI status is at F0BAR1+I/O Offset 1Ch[6:5].

SMI Source is ACPI. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was caused by an access (read

or write) to one of the ACPI registers (F1BAR1).

0: No.

1: Yes.

The next level (second level) of SMI status is at F1BAR0+I/O Offset 20h.

SMI Source is XpressAUDIO Subsystem. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was

caused by the audio subsystem.

0: No.

1: Yes.

The second level of status is found in F3BAR0+Memory Offset 10h/12h.

SMI Source is Power Management Event. (Read Only, Read Does Not Clear) Indicates whether or not an SMI was

caused by one of the power management resources (except for GP timers, UDEFx and PCI/ISA function traps which are

reported in bit 9).

0: No.

1: Yes.

The next level (second level) of SMI status is at F0 Index 84h/F4h-87h/F7h.

Offset 04h-05h

Second Level General Traps & Timers

Reset Value: 0000h

PME/SMI Status Mirror Register (RO)

The bits in this register contain second level status reporting. Top level status is reported at F1BAR0+I/O Offset 00h/02h[9].

Reading this register does not clear the SMI. For more information, see F1BAR0+I/O Offset 06h.

15:6

Reserved.

PCI/ISA Function Trap. Indicates whether or not an SMI was caused by a trapped PCI/ISA configuration cycle.

0: No.

1: Yes.

To enable SMI generation for:

— Trapped access to ISA Legacy I/O register space set F0 Index 41h[0] = 1.

— Trapped access to F1 register space set F0 Index 41h[1] = 1.

— Trapped access to F2 register space set F0 Index 41h[2] = 1.

— Trapped access to F3 register space set F0 Index 41h[3] = 1.

— Trapped access to F5 register space set F0 Index 41h[5] = 1.

SMI Source is Trapped Access to User Defined Device 3. Indicates whether or not an SMI was caused by a trapped I/O

or memory access to the User Defined Device 3 (F0 Index C8h).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 82h[6] = 1.

Table 5-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)

Bit

Description

SC1100 Datasheet(PDF) 210 Page - National Semiconductor (TI)

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