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Core Logic Module (Continued)

I/O Base Address Register (Bit 0 = 1)

31:2

Address Mask. Determines the size of the BAR.

— Every bit that is a 1 is programmable in the BAR.

— Every bit that is a 0 is fixed 0 in the BAR.

Since the address mask goes down to bit 2, the smallest I/O region is 4 bytes, however, the PCI Specification suggests not

using less than a 4 KB address range.

Reserved. Must be set to 0.

This bit must be set to 1, to indicate an I/O base address register.

Index 44h-47h

F5BAR1 Mask Address Register (R/W)

Reset Value: 00000000h

To use F5BAR1, the mask register should be programmed first. The mask register defines the size of F5BAR1 and whether the

accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.

Note:

Whenever a value is written to this mask register, F5BAR1 must also be written (even if the value for F5BAR1 has not

changed).

Index 48h-4Bh

F5BAR2 Mask Address Register (R/W)

Reset Value: 00000000h

To use F5BAR2, the mask register should be programmed first. The mask register defines the size of F5BAR2 and whether the

accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.

Note:

Whenever a value is written to this mask register, F5BAR2 must also be written (even if the value for F5BAR2 has not

changed).

Index 4Ch-4Fh

F5BAR3 Mask Address Register (R/W)

Reset Value: 00000000h

To use F5BAR3, the mask register should be programmed first. The mask register defines the size of F5BAR3 and whether the

accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.

Note:

Whenever a value is written to this mask register, F5BAR3 must also be written (even if the value for F5BAR3 has not

changed).

Index 50h-53h

F5BAR4 Mask Address Register (R/W)

Reset Value: 00000000h

To use F5BAR4, the mask register should be programmed first. The mask register defines the size of F5BAR4 and whether the

accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.

Note:

Whenever a value is written to this mask register, F5BAR4 must also be written (even if the value for F5BAR4 has not

changed).

31:4

Address Mask. Bits [31:24] must be set to FFh. Other bits should be set according to the specific system configuration.

Prefetchable. Should be set according to the specific system configuration.

2:1

Type. Should be set according to the specific system configuration.

Memory Space Indicator. Must be set to 0.

Index 54h-57h

F5BAR5 Mask Address Register (R/W)

Reset Value: 00000000h

To use F5BAR5, the mask register should be programmed first. The mask register defines the size of F5BAR5 and whether the

accessed offset registers are memory or I/O mapped. See F5 Index 40h (F5BAR0 Mask Address Register) above for bit descriptions.

Note:

Whenever a value is written to this mask register, F5BAR5 must also be written (even if the value for F5BAR5 has not

changed).

31:4

Address Mask. Bits [31:24] must be set to FFh. Other bits should be set according to the specific system configuration.

Prefetchable. Should be set according to the specific system configuration.

2:1

Type. Should be set according to the specific system configuration.

Memory Space Indicator. Must be set to 0.

Table 5-39. F5: PCI Header Registers for X-Bus Expansion (Continued)

Bit

Description

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