SC1100 datasheet(249/348 Pages) NSC

249 / 348 page

Revision 1.1

249

www.national.com

Core Logic Module (Continued)

Index 58h

F5BARx Initialized Register (R/W)

Reset Value: 00h

7:6

Reserved. Must be set to 0.

F5BAR5 Initialized. This bit indicates if F5BAR5 (F5 Index 24h) has been initialized.

At reset this bit is cleared (0). Writing F5BAR5 sets this bit to 1. If this bit is programmed to 0, the decoding of F5BAR5 is

disabled until either this bit is set to 1 or F5BAR5 is written (which causes this bit to be set to 1).

F5BAR4 Initialized. This bit indicates if F5BAR4 (F5 Index 28h) has been initialized.

At reset this bit is cleared (0). Writing F5BAR4 sets this bit to 1. If this bit is programmed to 0, the decoding of F5BAR4 is

disabled until either this bit is set to 1 or F5BAR4 is written (which causes this bit to be set to 1).

F5BAR3 Initialized. This bit indicates if F5BAR3 (F5 Index 1Ch) has been initialized.

At reset this bit is cleared (0). Writing F5BAR3 sets this bit to 1. If this bit is programmed to 0, the decoding of F5BAR3 is

disabled until either this bit is set to 1 or F5BAR3 is written (which causes this bit to be set to 1).

F5BAR2 Initialized. This bit indicates if F5BAR2 (F5 Index 18h) has been initialized.

At reset this bit is cleared (0). Writing F5BAR2 sets this bit to 1. If this bit is programmed to 0, the decoding of F5BAR2 is

disabled until either this bit is set to 1 or F5BAR2 is written (which causes this bit to be set to 1).

F5BAR1 Initialized. This bit indicates if F5BAR1 (F5 Index 14h) has been initialized.

At reset this bit is cleared (0). Writing F5BAR1 sets this bit to 1. If this bit is programmed to 0, the decoding of F5BAR1 is

disabled until either this bit is set to 1 or F5BAR1 is written (which causes this bit to be set to 1).

F5BAR0 Initialized. This bit indicates if F5BAR0 (F5 Index 10h) has been initialized.

At reset this bit is cleared (0). Writing F5BAR0 sets this bit to 1. If this bit is programmed to 0, the decoding of F5BAR0 is

disabled until either this bit is set to 1 or F5BAR0 is written (which causes this bit to be set to 1).

Index 59h

F5BARx Directed to Sub-ISA (R/W)

Reset: 00h

7:6

Reserved. Must be set to 0.

F5BAR5 Directed to Sub-ISA. Enables F5BAR5CS# to Sub-ISA.

0: F5BAR5 address range is not directed to Sub-ISA.

1: F5BAR5 address range is directed to Sub-ISA.

F5BAR4 Directed to Sub-ISA. Enables F5BAR4CS# to Sub-ISA.

0: F5BAR4 address range is not directed to Sub-ISA.

1: F5BAR4 address range is directed to Sub-ISA.

Reserved. Must be set to 0.

Index 5Ah-5Fh

Reserved

Reset Value: xxh

Index 60h-63h

Scratchpad: Usually used for Device Number (R/W)

Reset Value: 00000000h

BIOS writes a value, of the Device number. Expected value: 00001100h.

Index 64h-67h

Scratchpad: Usually used for Configuration Block Address (R/W)

Reset Value: 00000000h

BIOS writes a value, of the Configuration Block Address.

Index 68h-FFh

Reserved

Table 5-39. F5: PCI Header Registers for X-Bus Expansion (Continued)

Bit

Description

SC1100 Datasheet(PDF) 249 Page - National Semiconductor (TI)

SC1100 Datasheet(HTML) 249 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL