SC1100 datasheet(310/348 Pages) NSC

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Revision 1.1

Electrical Specifications (Continued)

Table 7-19. Register Transfer to/from Device

Symbol

Parameter

Mode 0

(ns)

Mode 1

(ns)

Mode 2

(ns)

Mode 3

(ns)

Mode 4

(ns)

Cycle time1 (min)

t0 is the minimum total cycle time, t2 is the minimum command active time, and t2i is the minimum command recovery

time or command inactive time. The actual cycle time equals the sum of the command active time and the command

inactive time. The three timing requirements of t0, t2, and t2i are met. The minimum total cycle time requirements is

greater than the sum of t2 and t2i. (This means that a host implementation can lengthen t2 and/or t2i to ensure that t0 is

equal to or greater than the value reported in the device’s IDENTIFY DEVICE data.)

600

383

240

180

120

Address valid to IDE_IOR[0:1]#/ IDE_IOW[0:1]#

setup (min)

IDE_IOR[0:1]#/IDE_IOW[0:1]# pulse width 8-bit1

(min)

290

t2i

IDE_IOR[0:1]#/IDE_IOW[0:1]# recovery time1

(min)

IDE_IOW[0:1]# data setup (min)

IDE_IOW[0:1]# data hold (min)

IDE_IOR[0:1]# data setup (min)

IDE_IOR[0:1]# data hold (min)

t6Z

IDE_IOR[0:1]# data TRI-STATE2 (max)

This parameter specifies the time from the rising edge of IDE_IOR[0:1]# to the time that the data bus is no longer driven

by the device (TRI-STATE).

IDE_IOR[0:1]#/IDE_IOW[0:1]# to address valid

hold (min)

tRD

Read Data Valid to IDE_IORDY[0:1] active (if

IDE_IORDY[0:1] initially low after tA (min)

IDE_IORDY[0:1] Setup time3

The delay from the activation of IDE_IOR[0:1]# or IDE_IOW[0:1]# until the state of IDE_IORDY[0,1] is first sampled. If

IDE_IORDY[0:1] is inactive, then the host waits until IDE_IORDY[0:1] is active before the PIO cycle is completed. If the

device is not driving IDE_IORDY[0:1] negated after activation (tA) of IDE_IOR[0:1]# or IDE_IOW[0:1]#, then t5 is met

and tRD is not applicable. If the device is driving IDE_IORDY[0:1] negated after activation (tA) of IDE_IOR[0:1]# or

IDE_IOW[0:1]#, then tRD is met and t5 is not applicable.

IDE_IORDY[0:1] Pulse Width (max)

1250

IDE_IORDY[0:1] Assertion to release (max)

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