SC1100 datasheet(120/348 Pages) NSC

120 / 348 page

www.national.com

120

Revision 1.1

Core Logic Module (Continued)

Physical Region Descriptor Table Address

Before the controller starts a master transfer it is given a

pointer to a Physical Region Descriptor Table. This pointer

sets the starting memory location of the Physical Region

Descriptors (PRDs). The PRDs describe the areas of mem-

ory that are used in the data transfer. The PRDs must be

aligned on a 4-byte boundary and the table cannot cross a

64 KB boundary in memory.

Primary and Secondary IDE Bus Master Registers

The IDE bus master registers for each channel (primary

and secondary) have an IDE Bus Master Command regis-

ter and Bus Master Status register. These registers and bit

formats are described in Table 5-36 on page 229.

Physical Region Descriptor Format

Each physical memory region to be transferred is

described by a Physical Region Descriptor (PRD) as illus-

trated in Table 5-1. When the bus master is enabled (Com-

mand register bit 0 = 1), data transfer proceeds until each

PRD in the PRD table has been transferred. The bus mas-

ter does not cache PRDs.

The PRD table consists of two DWORDs. The first DWORD

contains a 32-bit pointer to a buffer to be transferred. The

second DWORD contains the size (16 bits) of the buffer

and the EOT flag. The EOT bit (bit 31) must be set to indi-

cate the last PRD in the PRD table.

Programming Model

The following steps explain how to initiate and maintain a

bus master transfer between memory and an IDE device.

Software creates a PRD table in system memory.

Each PRD entry is 8 bytes long, consisting of a base

address pointer and buffer size. The maximum data

that can be transferred from a PRD entry is 64 KB. A

PRD table must be aligned on a 4-byte boundary. The

last PRD in a PRD table must have the EOT bit set.

Software loads the starting address of the PRD table

by programming the PRD Table Address register.

Software must fill the buffers pointed to by the PRDs

with IDE data.

Write 1 to the Bus Master Interrupt bit and Bus Master

Error (Status register bits 2 and 1) to clear the bits.

Set the correct direction to the Read or Write Control

bit (Command register bit 3).

Engage the bus master by writing a 1 to the Bus Mas-

ter Control bit (Command register bit 0).

The bus master reads the PRD entry pointed to by the

PRD Table Address register and increments the

address by 08h to point to the next PRD. The transfer

begins.

The bus master transfers data to/from memory

responding to bus master requests from the IDE

device. At the completion of each PRD, the bus mas-

ter’s next response depends on the settings of the

EOT flag in the PRD. If the EOT bit is set, then the IDE

bus master clears the Bus Master Active bit (Status

the transfer, the bus master sets the Bus Master Error

bit Status register bit 1).

Table 5-1. Physical Region Descriptor Format

DWORD

Byte 3

Byte 2

Byte 1

Byte 0

31 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9

Memory Region Physical Base Address [31:1] (IDE Data Buffer)

Reserved

Size [15:1]

SC1100 Datasheet(PDF) 120 Page - National Semiconductor (TI)

SC1100 Datasheet(HTML) 120 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL