SC1100 datasheet(123/348 Pages) NSC

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Core Logic Module (Continued)

5.2.5.1

Sub-ISA Bus Cycles

The ISA bus controller issues multiple ISA cycles to satisfy

PCI transactions that are larger than 16 bits. A full 32-bit

read or write results in two 16-bit ISA transactions or four 8-

bit ISA transactions. The ISA controller gathers the data

from multiple ISA read cycles and returns TRDY# to the

PCI bus.

SA[23:0] are a concatenation of ISA LA[23:17] and

SA[19:0] and perform equivalent functionality at a reduced

pin count.

Figure 5-2 shows the relationship between a PCI cycle and

the corresponding ISA cycle generated.

Note:

Not all signals described in Figure 5-2 are available

externally. See Section 2.4.5 "Sub-ISA Interface

Signals" on page 41 for more information about

which Sub-ISA signals are externally available on

the SC1100.

5.2.5.2

Sub-ISA Support of Delayed PCI Transac-

tions

Multiple PCI cycles occur for every slower ISA cycle. This

prevents slow PCI cycles from occupying too much band-

width and allows access to other PCI traffic. Figure 5-3 on

page 124 shows the relationship of PCI cycles to an ISA

cycle with PCI delayed transactions enabled.

Figure 5-2. Non-Posted Fast-PCI to ISA Access

Fast-PCI_CLK

ISACLK

FRAME#

IRDY#

TRDY#

AD[31:0] (Read)

RD#,WR#,IOR#,IOW#

AD[31:0] (Write)

BALE

STOP#

MEMR#,MEMW#

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