SC1100 datasheet(126/348 Pages) NSC

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126

Revision 1.1

Core Logic Module (Continued)

5.2.5.6

ROM Interface

The Core Logic module positively decodes memory

addresses

000F0000h-000FFFFFh

(64

KB)

and

FFFC0000h-FFFFFFFFh (256 KB) at reset. These memory

cycles cause the Core Logic module to claim the cycle, and

generate an ISA bus memory cycle with ROMCS#

asserted. The Core Logic module can also be configured to

respond to memory addresses FF000000h-FFFFFFFFh

(16 MB) and 000E0000h-000FFFFFh (128 KB).

8- or 16-bit wide ROM is supported. BOOT16 strap deter-

mines the width after reset. MCR[14,3] (Offset 34h) in the

General Configuration Block (see Table 3-2 on page 50 for

bit details) allows program control of the width.

Flash ROM is supported in the Core Logic module by

enabling the ROMCS# signal on write accesses to the

ROM region. Normally only read cycles are passed to the

ISA bus, and the ROMCS# signal is suppressed for write

cycles. When the ROM Write Enable bit (F0 Index 52h[1])

is set, a write access to the ROM address region causes a

write cycle to occur with MEMW#, WR# and ROMCS#

asserted.

5.2.5.7

PCI and Sub-ISA Signal Cycle Multiplexing

The SC1100 multiplexes most PCI and Sub-ISA signals on

the balls listed in Table 5-3, in order to reduce the number

of balls on the device. Cycle multiplexing is on a bus-cycle

by bus-cycle basis (see Figure 5-6 on page 127), where the

internal Core Logic PCI bridge arbitrates between PCI

cycles and Sub-ISA cycles. Other PCI and Sub-ISA signals

remain non-shared, however, some Sub-ISA signals may

be muxed with GPIO.

Sub-ISA cycles are only generated as a result of GX1 mod-

ule accesses to the following addresses or conditions:

• ROMCS# address range.

• DOCCS# address range.

• F5BAR4CS address range.

• F5BAR5CS address range.

• IOCS0# address range.

• IOCS1# address range.

• An I/O write to address 80h or to 84h.

If the Sub-ISA and PCI bus have more than four compo-

nents, the Sub-ISA components can be buffered using

74HCT245 or 74FCT245 type transceivers. The RD# (an

AND of IOR#, MEMR#) signal can be used as DIR control

while TRDE# is used as enable control.

Table 5-3. Cycle Multiplexed PCI / Sub-ISA Balls

PCI

Sub-ISA

Ball No.

AD0

E25

AD1

F26

AD2

F25

AD3

G26

AD4

G25

AD5

H26

AD6

H25

AD7

D24

AD8

E23

AD9

J26

AD10

A10

J25

AD11

A11

K25

AD12

A12

K26

AD13

A13

F23

AD14

A14

F24

AD15

A15

L26

AD16

A16

R25

AD17

A17

K24

AD18

A18

T26

AD19

A19

T25

AD20

A20

L24

AD21

A21

U26

AD22

A22

U25

AD23

A23

M24

AD24

V25

AD25

W26

AD26

N24

AD27

P24

AD28

W25

AD29

Y26

AD30

R24

AD31

Y25

C/BE0#

E24

C/BE1#

G24

C/BE2#

D10

R26

C/BE3#

D11

V26

PAR

D12

H24

TRDY#

D13

N25

IRDY#

D14

P26

STOP#

D15

M25

DEVSEL#

BHE#

N26

SC1100 Datasheet(PDF) 126 Page - National Semiconductor (TI)

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