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Revision 1.1

Core Logic Module (Continued)

5.2.4

Universal Serial Bus

The Core Logic module provides three complete, indepen-

dent USB ports. Each port has a Data "Negative" and a

Data "Positive" signal.

The USB ports are Open Host Controller Interface (Open-

HCI) compliant. The OpenHCI specification provides a reg-

ister-level description for a host controller, as well as

common industry hardware/software interface and drivers.

5.2.5

Sub-ISA Bus Interface

The Sub-ISA interface of the Core Logic module is an ISA-

like bus interface that is used by SC1100 to interface with

Boot Flash, M-Systems’ DiskOnChip or NAND EEPROM

and other I/O devices. The Core Logic module is the

default subtractive decoding agent and forwards all

unclaimed memory and I/O cycles to the internal ISA bus.

However, the Core Logic can be configured to ignore either

I/O, memory, or all unclaimed cycles (subtractive decode

disabled).

The Core Logic module does not support Sub-ISA refresh

cycles. The refresh toggle bit in Port B still exists for soft-

ware compatibility reasons.

The Sub-ISA interface includes the followings signals in

addition to the signals used for an ISA interface:

• IOCS0#/IOCS1#

— Asserted on I/O read/write transactions from/to a

programmable address range.

• DOCCS#

— Asserted on memory read/write transactions from/to

a programmable window.

• ROMCS#

— Asserted on memory read/write to upper 16 MB of

address space. Configurable via the ROM Mask

• F5BAR4CS#

— Asserted on memory read/write of up to 16 MB of

address space. Configurable via the F5BAR4

Sub-ISA Register (F5 Index 59h).

• F5BAR5CS#

—

Asserted on memory read/write of up to 16 MB of

address space. Configurable via the F5BAR5

Sub-ISA Register (F5 Index 59h).

• DOCR#

— DOCR# is asserted on memory read transactions

from DOCCS# window (i.e., when both DOCCS# and

MEMR# are active, DOCR# is active; otherwise, it is

inactive).

• DOCW

— DOCW is asserted on memory write transactions to

DOCCS window (i.e., when both DOCCS# and

MEMW# are active, DOCW is active; otherwise, it is

inactive).

• RD#, WR#

— The signals IOR#, IOW#, MEMR#, and MEMW# are

combined into two signals: RD# is asserted on I/O

read or memory read; WR# is asserted on I/O write

or memory write.

Memory

devices

that

use

ROMCS#,

DOCCS#,

F5BAR4CS#, or F5BAR5CS# as their chip select signal

can be configured to support an 8-bit or 16-bit data bus.

Such devices can also be configured as zero wait state

devices (regardless of the data bus width). Programming of

these features is via the Miscellaneous Configuration Reg-

ister (MCR) in the General Configuration Block. For MCR

I/O peripherals that use IOCS0# or IOCS1# as their chip

select signal can be configured to support an 8-bit or 16-bit

data bus. Such devices can also be configured as zero wait

state devices (for 8-bit peripherals) via the MCR register.

For MCR register bit descriptions, see Table 3-2 on page

50.

Other memory devices and I/O peripherals must be 8-bit

devices; their transactions can not be with zero wait states

The Boot Flash supported by the SC1100 can be up to 16

MB. It is supported with the ROMCS# signal.

All unclaimed memory and I/O cycles are forwarded to the

Internal ISA bus if subtractive decode is enabled.

The DiskOnChip chip select signal (DOCCS#) is asserted

on any memory read or memory write transaction from/to a

programmable address range. The address range is pro-

grammable via the DOCCS# Base Address and Control

registers (F0 Index 78h and 7Ch). The base address must

be on an address boundary, the size of the range.

Signal DOCCS# can also be used to interface to NAND

Flash devices together with signals DOCW# and DOCR#.

See application note Geode™ SC1200/SC2200/SC3200

IAOC Devices: External NAND Flash Memory Circuit for

details.

SC1100 Datasheet(PDF) 122 Page - National Semiconductor (TI)

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