DS26521 datasheet(193/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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TLS2

Transmit Latched Status Register 2 (HDLC)

191h

Bit #

Name

—

TFDLE

TUDR

TMEND

TLWMS

TNFS

—

TUDR

TMEND

TLWMS

TNFS

Default

Note: All bits in this register are latched and can create interrupts.

Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only). Set when the TFDL register has shifted out all 8

bits. Useful if the user wants to manually use the TFDL register to send messages, instead of using the HDLC or

BOC controller circuits.

Bit 3: Transmit FIFO Underrun Event (TUDR). Set when the transmit FIFO empties out without having seen the

TMEND bit set. An abort is automatically sent.

Bit 2: Transmit Message End Event (TMEND). Set when the transmit HDLC controller has finished sending a

message.

Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS). Set when the transmit 64-byte FIFO

empties beyond the low watermark as defined by the transmit low watermark bit (TLWM), rising edge detect of

TLWM.

Bit 0: Transmit FIFO Not Full Set Condition (TNFS). Set when the transmit 64-byte FIFO has at least one empty

byte available for write. Rising edge detect of TNF. Indicates change of state from full to not full.

TLS3

Transmit Latched Status Register 3 (Synchronizer)

192h

Bit #

Name

—

LOF

LOFD

Default

Note: Some bits in this register are latched and can create interrupts.

Bit 1: Loss of Frame (LOF). A real-time bit that indicates that the transmit synchronizer is searching for the sync

pattern in the incoming data stream.

Bit 0: Loss of Frame Synchronization Detect (LOFD). This latched bit is set when the transmit synchronizer is

searching for the sync pattern in the incoming data stream.

DS26521 Datasheet(PDF) 193 Page - Maxim Integrated Products

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