DS26521 datasheet(192/258 Pages) MAXIM

192 / 258 page

DS26521 Single T1/E1/J1 Transceiver

192 of 258

TLS1

Transmit Latched Status Register 1

190h

Bit #

Name

TESF

TESEM

TSLIP

TSLC96

TPDV

TMF

LOTCC

LOTC

TESF

TESEM

TSLIP

—

TAF

TMF

LOTCC

LOTC

Default

Note: All bits in this register are latched and can cause interrupts.

Bit 7: Transmit Elastic Store Full Event (TESF). Set when the transmit elastic store buffer fills and a frame is

deleted.

Bit 6: Transmit Elastic Store Empty Event (TESEM). Set when the transmit elastic store buffer empties and a

frame is repeated.

Bit 5: Transmit Elastic Store Slip Occurrence Event (TSLIP). Set when the transmit elastic store has either

repeated or deleted a frame.

Bit 4: Transmit SLC-96 Multiframe Event (TSLC96) (T1 Mode Only). When enabled by TCR2.6, this bit will set

once per SLC-96 multiframe (72 frames) to alert the host that new data may be written to the T1TSLC1:T1TSLC3

registers. See Section 8.9.4.4 for more information.

Bit 3 (T1 Mode): Transmit Pulse Density Violation Event (TPDV). Set when the transmit data stream does not

meet the ANSI T1.403 requirements for pulse density.

Bit 3 (E1 Mode): Transmit Align Frame Event (TAF). Set every 250

μs to alert the host that the E1TAF and

E1TNAF registers need to be updated.

Bit 2: Transmit Multiframe Event (TMF). In T1 mode, this bit is set every 1.5ms on D4 MF boundaries or every

3ms on ESF MF boundaries. In E1 operation, this but is set every 2ms (regardless if CRC-4 is enabled) on transmit

multiframe boundaries. Used to alert the host that signaling data needs to be updated.

Bit 1: Loss of Transmit Clock Condition Clear (LOTCC). Set when the LOTC condition has cleared (a clock has

been sensed at the TCLK pin).

Bit 0: Loss of Transmit Clock Condition (LOTC). Set when the TCLK pin has not transitioned for approximately

3 clock periods. Will force the LOTC bit high if enabled. This bit can be cleared by the host even if the condition is

still present. LOTC will remain high while the condition exists, even if the host has cleared the status bit. If enabled

by TIM1.0, the

INTB pin will transition low when this bit is set, and transition high when this bit is cleared (if no other

unmasked interrupt conditions exist).

DS26521 Datasheet(PDF) 192 Page - Maxim Integrated Products

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