DS26521 datasheet(196/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

196 of 258

TIM2

Transmit Interrupt Mask Register 2 (HDLC)

1A1h

Bit #

Name

—

TFDLE

TUDR

TMEND

TLWMS

TNFS

—

TUDR

TMEND

TLWMS

TNFS

Default

Bit 4: Transmit FDL Register Empty (TFDLE) (T1 Mode Only).

0 = interrupt masked

1 = interrupt enabled

Bit 3: Transmit FIFO Underrun Event (TUDR).

0 = interrupt masked

1 = interrupt enabled

Bit 2: Transmit Message End Event (TMEND).

0 = interrupt masked

1 = interrupt enabled

Bit 1: Transmit FIFO Below Low Watermark Set Condition (TLWMS).

0 = interrupt masked

1 = interrupt enabled

Bit 0: Transmit FIFO Not Full Set Condition (TNFS).

0 = interrupt masked

1 = interrupt enabled

TIM3

Transmit Interrupt Mask Register 3 (Synchronizer)

1A2h

Bit #

Name

—

LOFD

Default

Bit 0: Loss of Frame Synchronization Detect (LOFD).

0 = interrupt masked

1 = interrupt enabled

DS26521 Datasheet(PDF) 196 Page - Maxim Integrated Products

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