 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DS26521 Datasheet(PDF) 201 Page - Maxim Integrated Products |
|
|
|||||||||||||||||||||||||||||
DS26521 Datasheet(HTML) 201 Page - Maxim Integrated Products |
|
|
201 / 258 page  DS26521 Single T1/E1/J1 Transceiver 201 of 258 Register Name: THSCS1, THSCS2, THSCS3, THSCS4 Register Description: Transmit Hardware-Signaling Channel Select Registers 1 to 4 Register Address: 1C8h, 1C9h, 1CAh, 1CBh Bit # (MSB) 7 6 5 4 3 2 1 0 (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 THSCS1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 THSCS2 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 THSCS3 Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 THSCS4* (E1 Mode Only) Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Transmit Hardware-Signaling Channel Select for Channels 1 to 32 (CH[1:32]). These bits determine which channels have signaling data inserted from the TSIG pin into the TSER PCM data. 0 = do not source signaling data from the TSIG pin for this channel 1 = source signaling data from the TSIG pin for this channel *Note that THSCS4 is only used in 2.048MHz backplane applications. Register Name: TGCCS1, TGCCS2, TGCCS3, TGCCS4 Register Description: Transmit Gapped-Clock Channel Select Registers 1 to 4 Register Address: 1CCh, 1CDh, 1CEh, 1CFh Bit # (MSB) (LSB) CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 TGCCS1 CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9 TGCCS2 CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17 TGCCS3 Name CH32 CH31 CH30 CH29 CH28 CH27 CH26 CH25 (F-bit) TGCCS4* (E1 Mode Only) Default 0 0 0 0 0 0 0 0 Bits 7 to 0: Transmit Gapped-Clock Channel Select Channels 1 to 32 (CH[1:32]). 0 = no clock is present on TCHCLK during this channel time 1 = force a clock on TCHCLK during this channel time. The clock will be synchronous with TCLK if the elastic store is disabled, and synchronous with TSYSCLK if the elastic store is enabled. *Note that TGCCS4 has two functions: When 2.048MHz backplane mode is selected, this register allows the user to enable the gapped clock on TCHCLK for any of the 32 possible backplane channels. When 1.544MHz backplane mode is selected, the LSB of this register determines whether or not a clock is generated on TCHCLK during the F-bit time: TGCCS4.0 = 0: Do not generate a clock during the F-bit TGCCS4.0 = 1: Generate a clock during the F-bit In this mode, TGCCS4.1 to TGCCS4.7 should be set to 0. |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
