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GX1 Datasheet(PDF) 122 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 122 Page - National Semiconductor (TI) |
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122 / 247 page ![]() www.national.com 122 Revision 1.0 Integrated Functions (Continued) SDRAM Refresh Cycle Figure 4-7 shows a SDRAM auto refresh cycle. The mem- ory controller always precedes the refresh cycle with a PRE command to all banks. Page Miss Figure 4-8 shows a READ/WRT command after a page miss cycle. In order to program the new row address, a PRE command must be issued followed by an ACT com- mand. Figure 4-7. Auto Refresh Cycle Figure 4-8. READ/WRT Command to a New Row Address SDCLK CS# RAS# CAS# WE# MA[10] SDCLK COMMAND ADDRESS tRP tRCD PRE NOP NOP ACT NOP NOP R/W NOP ROW COL BA |
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