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GX1 Datasheet(PDF) 125 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 125 Page - National Semiconductor (TI) |
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125 / 247 page ![]() Revision 1.0 125 www.national.com Integrated Functions (Continued) 4.4 GRAPHICS PIPELINE The graphics pipeline of the GX1 processor contains a 2D graphics accelerator. This hardware accelerator has a Bit- BLT/vector engine which dramatically improves graphics performance when rendering and moving graphical objects. Overall operating system performance is improved as well. The accelerator hardware supports pattern gener- ation, source expansion, pattern/source transparency, and 256 ternary raster operations. The block diagram of the graphics pipeline is shown in Figure 4-11. 4.4.1 BitBLT/Vector Engine BLTs are initiated by writing to the GP_BLT_MODE regis- ter, whichspecifies thetypeofsourcedata(none, frame buffer, or BLT buffer), the type of the destination data (none, frame buffer, or BLT buffer), and a source expansion flag. Vectors are initiated by writing to the GP_VECTOR_MODE register (GX_BASE+8204h), which specifies the direction of the vector and a “read destination data” flag.Ifthe flag is set, the hardware will read destination data along the vec- tor and store it temporarily in the BLT Buffer 0. The BLT buffers use a portion of the L1 cache, called “scratchpad RAM”, to temporarily store source and destina- tion data, typically on a scan line basis. See Section 4.1.4.2 “Scratchpad RAM Utilization” on page 100 for an explana- tion of scratchpad RAM. The hardware automatically loads frame-buffer data (source or destination) into the BLT buff- ers for each scan line. The driver is responsible for making sure that this does not overflow the memory allocated for the BLT buffers. When the source data is a bitmap, the hardware loads the data directly into the BLT buffer at the beginning of the BLT operation. Figure 4-11. Graphics Pipeline Block Diagram Pattern Hardware Raster Operation Output Aligner BE PAT SRC DST BE Internal Bus Interface Unit Graphics Scratchpad RAM BitBLT Buffers and Memory X-Bus C-Bus Pipeline BE = Byte Enable PAT = Pattern Data SRC = Source Data DST = Destination Data Output Aligner Source Expansion Control Logic DRAM Interface Register Access Controller Key: |
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