GX1 datasheet(123/247 Pages) NSC

Part #	GX1

Description	Processor Series Low Power Integrated x86 Solution

PDF	247 Pages

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Manufacturer	NSC [National Semiconductor (TI)]

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Integrated Functions (Continued)

4.3.7

SDRAM Interface Clocking

The GX1 processor drives the SDCLK to the SDRAMs; one

for each DIMM bank. All the control, data, and address sig-

nals driven by the memory controller are sampled by the

SDRAM at the rising edge of SDCLK. SDCLKOUT is a ref-

erence signal used to generate SDCLKIN. Read data is

sampled by the memory controller at the rising edge of

SDCLKIN.

The delay for SDCLKIN from SDCLKOUT must be

designed so that it lags the SDCLKs at the DRAM by

approximately 1 ns (check application notes for additional

information). The delay should also include the SDCLK

transmission line delay. All four SDCLK traces on the board

should be the same length, so there is no skew between

them. These guidelines allow the memory interface to

operate at a higher performance.

Figure 4-9. SDCLKIN Clocking

DIMM

SDCLK[3:0]

Delay

SDCLKOUT

SDCLKIN

Geode™ GX1

SDCLK0

SDCLK1

SDCLK2

SDCLK3

Processor

GX1 Datasheet(PDF) 123 Page - National Semiconductor (TI)