GX1 datasheet(202/247 Pages) NSC

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202

Revision 1.0

Electrical Specifications (Continued)

Figure 6-9. Output Valid Timing

Figure 6-10. Setup and Hold Timings - Read Data In

Table 6-17. SDRAM Interface Signals (Refer to Figures 6-9 and 6-10)

Symbol

Parameter

Min

Max

Unit

RASA#, RASB#, CASA#, CASB#,

WEA#, WEB#, CKEA, CKEB, DQM[7:0],

CS[3:0]# Ouput Valid from SDCLK[3:0]

t1 Min = z – 1.31

t1 Max= z+ 0.51

MA[12:0], BA[1:0] Output Valid from

SDCLK[3:0]

t2 Min = z – 1.21

t2 Max= z+ 0.61

MD[63:0] Output Valid from SDCLK[3:0]

t2 Min = z – 1.31

t3 Max= z+ 1.11

MD[63:0] Read Data in Setup to

SDCLK_IN

0.6

MD[63:0] Read Data Hold to SDCLK_IN

2.1

Calculation of minimum and maximum values of t1, t2, and t3: (see Figure 4-10 on page 124)

x =shift value applied to SHFTSDCLK field where SHFTSDCLK field = GX_BASE+8404h[5:3].

y = core clock period ÷ 2

z= (x *y)

Equation Example:

A 200 MHz GX1 processor interfacing with a 66 MHz SDRAM bus, having a shift value of 2:

x= 2

core clock period = 1/(200 MHz) = 5 ns

y= 5 ÷ 2

t1 Min = (2 * (5 ÷ 2)) – 1.3 = 3.7 ns

t1 Max = (2 * (5 ÷ 2)) + 0.5 = 5.5 ns

SDCLK[3:0]

CNTRL, MA[12:0],

BA[1:0], MD[63:0]

t1, t2, t3

Valid

SDCLK_IN

MD[63:0]

Read Data In

Data Valid

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