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GX1 Datasheet(PDF) 203 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 203 Page - National Semiconductor (TI) |
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203 / 247 page ![]() Revision 1.0 203 www.national.com Electrical Specifications (Continued) Figure 6-11. Graphics Port Timing Table 6-18. Video Interface Signals (Refer to Figures 6-11 through 6-13) Symbol Parameter Min Max Unit t1 PCLK Period 6.3 40 ns t2 PCLK High Time 2.8 ns t3 PCLK Low Time 2.8 ns t4 PIXEL[17:0], CRT_HSYNC, CRT_VSYNC, FP_HSYNC, FP_VSYNC, ENA_DISP Valid Delay from PCLK Rising Edge 24 ns t5 VID_CLK Period 6.7 ns t6 VID_RDY Setup to VID_CLK Rising Edge 5 ns t7 VID_RDY Hold to VID_CLK Rising Edge 2 ns t8 VID_VAL, VID_DATA[7:0] Valid Delay from VID_CLK Rising Edge 2 4 ns t9 DCLK Period 6.3 ns t10 DCLK Rise/Fall Time 2 ns tcyc DCLK Duty Cycle 40 60 % t1 t2 t3 t4 PCLK PIXEL[17:0], CRT_HSYNC, CRT_VSYNC, FP_HSYNC, FP_VSYNC, ENA_DISP Data Valid Data Valid |
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