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GX1 Datasheet(PDF) 201 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 201 Page - National Semiconductor (TI) |
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201 / 247 page ![]() Revision 1.0 201 www.national.com Electrical Specifications (Continued) Figure 6-7. Output Timing Figure 6-8. Input Timing Table 6-16. PCI Interface Signals (Refer to Figures 6-7 and 6-8) Symbol Parameter Min Max Unit tVAL1 Delay Time, SYSCLK to Signal Valid for Bused Signals 2 11 ns tVAL2 Delay Time, SYSCLK to Signal Valid for GNT#1, 2 29 ns tON Delay Time, Float to Active 2 ns tOFF Delay Time, Active to Float 28 ns tSU1 Input Setup Time for Bused Signals 7 ns tSU2 Input Setup Time for REQ#1, 2 6ns tH Input Hold Time to SYSCLK 0 ns 1. GNT# and REQ# are point-to-point signals. All other PCI interface signals are bused. Refer to Chapter 4 of PCI Local Bus Specification, Revision 2.1, for more detailed information. 2. Maximum timings are improved over the PCI Local Bus Specification, Revision 2.1. This allows a PAL or some other circuit to use a REQ/GNT pair to expand the number of REQ/GNT pairs available to the system. SYSCLK TRI-STATE® OUTPUT OUTPUT tVAL1,2 tOFF tON SYSCLK INPUT tH tSU1,2 |
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