GX1 datasheet(239/247 Pages) NSC

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Instruction Set (Continued)

8.5

MMX INSTRUCTION SET

The CPU is functionally divided into the FPU unit, and the

integer unit. The FPU has been extended to process both

MMX instructions and floating point instructions in parallel

with the integer unit.

For example, when the integer unit detects an MMX

instruction, the instruction passes to the FPU unit for exe-

cution. The integer unit continues to execute instructions

while the FPU unit executes the MMX instruction. If another

MMX instruction is encountered, the second MMX instruc-

tion is placed in the MMX queue. Up to four MMX instruc-

tions can be queued.

The MMX instruction set is summarized in Table 8-31. The

abbreviations used in the table are listed Table 8-30.

Table 8-30. MMX Instruction Set Table Legend

Abbreviation

Description

<----

Result written.

[11 mm reg]

Binary or binary groups of digits.

One of eight 64-bit MMX registers.

reg

A general purpose register.

<--sat--

If required, the resultant data is saturated to

remain in the associated data range.

<--move--

Source data is moved to result location.

[byte]

Eight 8-bit BYTEs are processed in parallel.

[word]

Four 16-bit WORDs are processed in paral-

lel.

[dword]

Two 32-bit DWORDs are processed in par-

allel.

[qword]

One 64-bit QWORD is processed.

[sign xxx]

The BYTE, WORD, DWORD or QWORD

most significant bit is a sign bit.

mm1, mm2

MMX Register 1, MMX Register 2.

mod r/m

Mod and r/m byte encoding (Table 8-15 on

page 217).

pack

Source data is truncated or saturated to

next smaller data size, then concatenated.

packdw

Pack two DWORDs from source and two

DWORDs from destination into four

WORDs in the destination register.

packwb

Pack four WORDs from source and four

WORDs from destination into eight BYTEs

in the destination register.

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