BT8376EPF datasheet(104/323 Pages) CONEXANT

104 / 323 page

2.0 Circuit Description

Bt8370/8375/8376

2.9 Transmit Line Interface Unit

Fully Integrated T1/E1 Framer and Line Interface

2-76

Conexant

N8370DSE

2.9.2 Transmit Phase Lock Loop

The Transmit Phase Lock Loop (TPLL) operates at a nominal rate of either 1.544

MHz or 2.048 MHz, selected by T1/E1N [CR0; addr 001]. The pull-in and

hold-in range of the TPLL is

±200 ppm. The TPLL produces the transmit clock

(TCKO) and an 8x clock that is used by the pulse shape block to generate the

AMI pulses from TCKI clock mux, or JCLK.

2.9.2.1 Clock Reference

The TPLL reference clock is provided on the TCKO pin. If the jitter attenuator is

enabled in the transmit direction [JDIR; addr 002], TCKO is the dejittered TCKI

clock, or JCLK (if CLAD is enabled); otherwise, TCKO equals TCKI. The TCKI

source is selected by TCKI[1:0] [CMUX; addr 01A]. TCKI can have the

following selections: Recovered Receive Clock (RCKO), Receive System Bus

Clock Input (RSBCKI), Clock Rate Adapter Output (CLADO), or an external

clock, which is provided on the TCKI pin. The input clock jitter tolerance of the

TPLL is illustrated in Figure 2-40.

Figure 2-40. TPLL Input Clock Jitter Tolerance

10 k

1.0 k

10.0

100.0

1.0

0.1

1.0

10.0

100.0

1.0 k

10.0 k

100.0 k

TPLL

Sine Wave Jitter Frequency (Hz) [Log Scale]

138 UI

28 UI

40 dB/Decade

2 UI

TR 62411

0.2 UI

BT8376EPF Datasheet(PDF) 104 Page - Synaptics Incorporated.

BT8376EPF Datasheet(HTML) 104 Page - Synaptics Incorporated.

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