BT8376EPF datasheet(154/323 Pages) CONEXANT

154 / 323 page

3.0 Registers

Bt8370/8375/8376

3.6 Primary Control and Status Registers

Fully Integrated T1/E1 Framer and Line Interface

3-36

Conexant

N8370DSE

01A—Clock Input Mux (CMUX)

RSBCKI[1:0]

RSBCKI Source Select—The internal clock mux selects 1 of four clock signals for application

to the RSB timebase. RSBCKI input pin is ignored when a clock source other than RSBCKI is

selected.

TSBCKI[1:0]

TSBCKI Source Select—The internal clock mux selects 1 of four clock signals for application

to the TSB timebase. TSBCKI input pin is ignored when a clock source other than TSBCKI is

selected. If TSLIP is bypassed [TSB_CR; addr 0D4], TSBCKI is not used, and the transmit

data on TPCMI must be aligned with the TCKI source selected below.

CLADI[1:0]

CLADI Source Select—The internal clock mux selects 1 of four clock signals. The selected

clock signal acts as a CLAD input timing reference when the CLAD is enabled [CEN; addr

090]. CLADI input pin is ignored whenever a clock source other than CLADI is selected.

RSBCKI[1]

RSBCKI[0]

TSBCKI[1]

TSBCKI[0]

CLADI[1]

CLADI[0]

TCKI[1]

TCKI[0]

RSBCKI[1:0]

RSBCKI

Source

Notes

RSBCKI

Normal RSB timebase

TSBCKI

RSB slaved to TSB

CLADI

RSB slaved to CLAD input pin

CLADO

Internal CLAD (before output

buffer).

TSBCKI[1:0]

TSBCKI

Source

Notes

TSBCKI

Normal TSB timebase

RSBCKI

TSB slaved to RSB

CLADI

TSB slaved to CLAD input

CLADO

Internal CLAD (before output

buffer).

none

When TSLIP is bypassed

CLADI[1:0]

CLADI

Source

Notes

CLADI

Normal CLAD input timing

RCKO

Internal RCKO (before output

buffer).

TSBCKI

CLAD slaved to TSB

TCKI

CLAD slaved to transmit

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