BT8376EPF datasheet(201/323 Pages) CONEXANT

201 / 323 page

Bt8370/8375/8376

Fully Integrated T1/E1 Framer and Line Interface

3.14 Clock Rate Adapter Registers

N8370DSE

Conexant

3-83

3.14 Clock Rate Adapter Registers

Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no

effect.

090—Clock Rate Adapter Configuration (CLAD_CR)

CEN

Enable CLAD Phase Detector—When active, the CPHASE detector compares the CLAD

reference (CLADI/RSCALE) to the CLAD variable (CLADV/VSCALE), and sends the

resulting phase error information to the NCO. When inactive, the CLADI signal is ignored and

JEN or JFREE [addr 002] selects the input timing reference.

XSEL[2:0]

Line Rate Multiple Select—The CLAD divider chain outputs (CLADO and CLADV) can be

programmed to operate at 20 to 23 times (1 X to 32 X) the T1/E1 line rate. XSEL chooses the

multiplier. This is applicable only when OSEL or VSEL [addr 091] selects the multiplier

output.

CEN

XSEL[2]

XSEL[1]

XSEL[0]

LFGAIN[3]

LFGAIN[2]

LFGAIN[1]

LFGAIN[0]

CEN

JEN

JFREE

JDIR

CLAD Input Timing Reference

REFCKI = Free running 10 MHz clock

REFCKI = Free running 10 MHz clock with transmit

JAT

REFCKI = Free running 10 MHz clock with receive

JAT

TXCLK = TCKI or ACKI per AISCLK [addr 068]

RXCLK = RPLL or RCKI per RDIGI [addr 020]

CLADI = System clock, bypass JAT elastic store

CLADI = System clock, with transmit JAT

CLADI = System clock, with receive JAT

NOTE:

JCLK always operates at T1 or E1 line rate selected by T1/E1N.

XSEL

Output (kHz)

T1/E1N = 0

Output (kHz)

T1/E1N = 1

Line Rate Multiplier

2048

1544

4096

3088

8192

6176

16384

12352

4, 5, 6, 7

——

Reserved

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