BT8376EPF datasheet(228/323 Pages) CONEXANT

228 / 323 page

Bt8370/8375/8376

3.16 Data Link Registers

Fully Integrated T1/E1 Framer and Line Interface

3-110

Conexant

N8370DSE

0BA—DLINK Test Configuration (DL_TEST1)

Data link test registers [addr 0BA-0BE] are for CONEXANT production test. Set to 0 for normal operation.

DL_TEST1[3]

Clock Test—Zero for normal operation, where clocks are controlled by DL1_CTL and

DL2_CTL [addr 0A6, 0B1]. When active-high, clocks are enabled.

DL_TEST1[2]

Shadow Select—Report shadow pointers instead of normal read/write pointers.

DL_TEST1[1, 0]

FIFO Select: 00 = RDL1; 01 = RDL2; 10 = TDL1; 11 = TDL2

0BB—DLINK Test Status (DL_TEST2)

DL_TEST2[5:0]

Read or Shadow Read Pointer—Reports selected FIFO read pointer current address.

0BC—DLINK Test Status (DL_TEST3)

DL_TEST3[5:0]

Write or Shadow Write Pointer—Specifies selected FIFO write pointer address.

0BD—DLINK Test Control #1 or Configuration #2 (DL_TEST4)

DL_TEST4[6]

TFIFO1 Read Clear—Force transmit FIFO read pointer to empty.

DL_TEST4[5]

TFIFO1 Write Clear—Force transmit FIFO write pointer to empty.

DL_TEST4[4]

TFIFO1 Write—MPU data goes to specified write pointer address.

DL_TEST4[3]

RFIFO1 Read Clear—Force receive FIFO read pointer to empty state (flush).

DL_TEST4[2]

RFIFO1 Write Clear—Force receive FIFO write pointer to empty state (flush).

DL_TEST4[1]

RFIFO1 Write—MPU data goes to specified write pointer address.

DL_TEST4[0]

RFIFO1 Bypass—Pipe receive data.

————

DL_TEST1[3]

DL_TEST1[2]

DL_TEST1[1]

DL_TEST1[0]

——

DL_TEST2[5]

DL_TEST2[4]

DL_TEST2[3]

DL_TEST2[2]

DL_TEST2[1]

DL_TEST2[0]

——

DL_TEST3[5]

DL_TEST3[4]

DL_TEST3[3]

DL_TEST3[2]

DL_TEST3[1]

DL_TEST3[0]

—

DL_TEST4[6]

DL_TEST4[5]

DL_TEST4[4]

DL_TEST4[3]

DL_TEST4[2]

DL_TEST4[1]

DL_TEST4[0]

BT8376EPF Datasheet(PDF) 228 Page - Synaptics Incorporated.

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