BT8376EPF datasheet(230/323 Pages) CONEXANT

230 / 323 page

Bt8370/8375/8376

3.17 System Bus Registers

Fully Integrated T1/E1 Framer and Line Interface

3-112

Conexant

N8370DSE

3.17 System Bus Registers

Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no effect.

0D0—System Bus Interface Configuration (SBI_CR)

X2CLK

Enable Times 2 Clocks—X2CLK modifies the number of RSB/TSB clock cycles used to clock

a single data bit onto RSB and TSB. When X2CLK is active, two RSBCKI/TSBCKI clock

cycles occur for each RPCMO, RSIGO, SIGFRZ, TPCMI, and TSIGI bit. The FSYNC and

MSYNC signals remain at the full 1x RSBCKI/TSBCKI clock rate.

0 = RSB/TSB signals at RSBCKI/TSBCKI

1 = Two SBCKI clock cycles per SBI bit (except FSYNC and MSYNC).

SBI_OE

Enable System Bus Outputs—Places RPCMO, RSIGO, RINDO, and SIGFRZ output buffers

under the control of the RSB timebase. SBI_OE also places the TINDO output buffer under

the control of TSB timebase. Inactive (low) forces SBI output buffers to a high-impedance

state. Power-on and RESET [addr 001] force SBI_OE to an inactive state to avoid bus

contention on devices that share system bus connections.

0 = SBI outputs forced to high-impedance state

1 = SBI outputs controlled by respective RSB or TSB timebase

EMF

Embedded Framing—During T1 mode, EMF controls placement of T1 framing bits on

RPCMO and the sampling of T1 framing bits from TPCMI. EMF supports system buses that

carry T1 frames but operate above T1 line rate. EMF allows the system bus to transport and

maintain 193-bit frame integrity while T1 data is passed through RSLIP and/or TSLIP buffers.

0 = G.802 embedded format

1 = Reserved

X2CLK

SBI_OE

EMF

EMBED

SBI[3]

SBI[2]

SBI[1]

SBI[0]

BT8376EPF Datasheet(PDF) 230 Page - Synaptics Incorporated.