BT8376EPF datasheet(231/323 Pages) CONEXANT

231 / 323 page

Bt8370/8375/8376

Fully Integrated T1/E1 Framer and Line Interface

3.17 System Bus Registers

N8370DSE

Conexant

3-113

EMBED

EMBED instructs the transmit framer (refer to [TABORT; addr 071] to align TX timebase with

respect to frame and multiframe alignment embedded in TXDATA, the transmit line rate data

output from TSLIP. If TSLIP is enabled, EMBED is inactive, and overhead is bypassed, TX

timebase is not guaranteed to align to TXDATA, and bypassed overhead cannot reliably pass

through TSLIP. EMBED is applicable to all system bus modes.

SBI[3:0]

System Bus Interface mode—Defines transmit and receive system bus data format. System

buses operate in one of nine basic formats which differ in the number of total available data

time slots and the associated system bus clock rate. If the total time slots are a multiple of 32,

SBI also defines which bus group of 32 byte-interleaved time slots are assigned to the

respective device.

EMBED

T1/E1N

Embedded Framing Mode

Transmit framer searches TPCMI

TS0 Embedded; search TXDATA

G.802; search TXDATA

NOTE(S):

Embedded F-bits reach TX output only if frame formatter [TFRM;

addr 072] is in Bypass or Transparent mode.

TS0 Embedded The offline framer examines TXDATA to align TX timebase to

the embedded FAS pattern. If MFAS is also enabled

[TFRAME; addr 070], the transmit online framer examines

TXDATA to align TX timebase to the embedded MFAS pattern.

While EMBED is active, TXDATA output is monitored, and

transmit frame errors are reported in ISR0 [addr 00B].

Embedded TS0 supports E1 overhead bypass options for

applications where TSLIP buffer is enabled.

G.802

Embedded

Automatically supports ITU–T Recommendation G.802, which

defines frame format conversion between T1 and E1 line rates

by locating T1 F-bits in Bit 1 of time slot 26 of each system bus

frame. G.802 embedded mode is applicable for system buses

that are 1x, 2x, or 4x multiples of the E1 line rate. Full

implementation of G.802 also requires the processor to program

TS0, TS16, and TS26–TS31 as unassigned system bus time

slots [SBCn; addr 0E0–0FF].

SBI[3:0]

Mode

Clock (Kobe)

Total Time Slots

Bus Group

0000

128A

8192

128

Group 0

0001

128B

8192

128

Group 1

0010

128C

8192

128

Group 2

0011

128D

8192

128

Group 3

0100

64A

4096

Group 0

0101

64B

4096

Group 1

0110

2048

—

0111

1544

24 + F-bit

—

1000

1536

—

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