SC1100 datasheet(181/348 Pages) NSC

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Core Logic Module (Continued)

ACPI Timer SMI. Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR0+I/O Offset 1Ch or

F1BAR1+I/O Offset 1Ch).

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[0].

THRM# SMI. Allow SMI generation on assertion of THRM# (ball AE15).

0: Disable.

1: Enable.

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[6].

Reserved. Must be set to 0.

General Purpose Timer 2 Enable. Turn on GP Timer 2 Count Register (F0 Index 8Ah) and generate an SMI when the

timer expires.

0: Disable.

1: Enable.

This idle timer is reloaded from the assertion of GPIO7 (if programmed to do so). GP Timer 2 programming is at F0 Index

8Bh[5,3,2].

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].

Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[1].

General Purpose Timer 1 Enable. Turn on GP Timer 1 Count Register (F0 Index 88h) and generate an SMI when the timer

expires.

0: Disable.

1: Enable.

This idle timer’s load is multi-sourced and gets reloaded any time an enabled event (F0 Index 89h[6:0]) occurs.

GP Timer 1 programming is at F0 Index 8Bh[4].

Top level SMI status is reported at F1BAR0+I/O Offset 00h/02h[9].

Second level SMI status is reported at F1BAR0+I/O Offset 04h/06h[0].

Index 84h

Second Level PME/SMI Status Mirror Register 1 (RO)

Reset Value: 00h

The bits in this register are used for the second level of status reporting. The top level is reported at F1BAR0+I/O Offset 00h/02h[0].

This register is called a "mirror" register since an identical register exists at F0 Index F4h. Reading this register does not clear the status,

while reading its counterpart at F0 Index F4h clears the status at both the second and the top levels.

7:3

Reserved. Reads as 0.

GPWIO2 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO2 pin.

0: No.

1: Yes.

To enable SMI generation:

1) Ensure that GPWIO2 is enabled as an input: F1BAR1+I/O Offset 15h[2] = 0.

2) Set F1BAR1+I/O Offset 15h[6] to 1.

GPWIO1 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO1 pin.

0: No.

1: Yes.

To enable SMI generation:

1) Ensure that GPWIO1 is enabled as an input: F1BAR1+I/O Offset 15h[1] = 0.

2) Set F1BAR1+I/O Offset 15h[5] to 1.

GPWIO0 SMI Status. Indicates whether or not an SMI was caused by a transition on the GPWIO0 pin.

0: No.

1: Yes.

To enable SMI generation:

1) Ensure that GPWIO0 is enabled as an input: F1BAR1+I/O Offset 15h[0] = 0.

2) Set F1BAR1+I/O Offset 15h[4] to 1.

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

Description

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