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182

Revision 1.1

Core Logic Module (Continued)

Index 85h

Second Level PME/SMI Status Mirror Register 2 (RO)

Reset Value: 00h

The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].

This register is called a “Mirror” register since an identical register exists at F0 Index F5h. Reading this register does not clear the status,

while reading its counterpart at F0 Index F5h clears the status at both the second and top levels.

Reserved. Reads as 0.

User Defined Device Idle Timer 3 Timeout. Indicates whether or not an SMI was caused by expiration of User Defined

Device 3 Idle Timer Count Register (F0 Index A4h).

0: No

1: Yes

To enable SMI generation, set F0 Index 81h[6] to 1.

User Defined Device Idle Timer 2 Timeout. Indicates whether or not an SMI was caused by expiration of User Defined

Device 2 Idle Timer Count Register (F0 Index A2h).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 81h[5] to 1.

User Defined Device Idle Timer 1 Timeout. Indicates whether or not an SMI was caused by expiration of User Defined

Device 1 Idle Timer Count Register (F0 Index A0h).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 81h[4] to 1.

Keyboard/Mouse Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Keyboard/Mouse Idle

Timer Count Register (F0 Index 9Eh).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 81h[3] to 1.

Parallel/Serial Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Parallel/Serial Port Idle

Timer Count Register (F0 Index 9Ch).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 81h[2] to 1.

Floppy Disk Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Floppy Disk Idle Timer

Count Register (F0 Index 9Ah).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 81h[1] to 1.

Primary Hard Disk Idle Timer Timeout. Indicates whether or not an SMI was caused by expiration of Primary Hard Disk

Idle Timer Count Register (F0 Index 98h).

0: No.

1: Yes.

To enable SMI generation, set F0 Index 81h[0] to 1.

Index 86h

Second Level PME/SMI Status Mirror Register 3 (RO)

Reset Value: 00h

The bits in this register contain second level status reporting. Top level status is reported in F1BAR0+I/O Offset 00h/02h[0].

This register is called a “Mirror” register since an identical register exists at F0 Index F6h. Reading this register does not clear the status,

while reading its counterpart at F0 Index F6h clears the status at both the second and top levels.

Reserved. Reads as 0.

Secondary Hard Disk Access Trap SMI Status. Indicates whether or not an SMI was caused by a trapped I/O access to

the secondary hard disk.

0: No.

1: Yes.

To enable SMI generation, set F0 Index 83h[6] to 1.

Table 5-29. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support (Continued)

Bit

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