SC1100 datasheet(281/348 Pages) NSC

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Electrical Specifications (Continued)

7.1.3

Operating Conditions

Table 7-2 lists the power supplies of the SC1100 and provides the device operating conditions.

Note:

All power sources must be connected to the SC1100,

even if the function is not used.

Voltages must be applied according to the sequence

set forth in Section 7.3.12 on page 339.

VSBL and VCORE must adhere at all times to the follow-

ing requirement: VSBL > VCORE.

The power planes of the SC1100 can be turned on or

off. For more information, see Section 5.2.9 "Power

Management Logic" on page 134.

It is recommended that the voltage difference between

VCORE and VSBL be less than 0.25V in order to reduce

leakage current. If the voltage difference exceeds

0.25V, excessive leakage current is used in gates that

are connected on the boundary between voltage

domains.

It is recommended that the voltage difference between

VIO and VSB be less than 0.25V in order to reduce

leakage current. If the voltage difference exceeds

0.25V, excessive leakage current is used in gates that

are connected on the boundary between voltage

domains.

VSB, VSBL and VBAT must be on if any other voltage is

applied. VSB and VBAT voltages can be applied sepa-

rately. See Section 7.3.12 "Power-Up Sequencing" on

page 339.

Table 7-2. Operating Conditions

Symbol1

For VIH (Input High Voltage), VIL (Input Low Voltage), IOH (Output High Current), and IOL (Output Low Current) operating

conditions refer to Section 7.2 "DC Characteristics" on page 286.

Parameter

Min

Typ

Max

Unit

Comments

Operating case temperature.

AVCCUSB

Analog power supply. Powers internal ana-

log circuits and some external signals (see

Table 7-3).

3.135

3.3

3.465

VBAT

Battery supply voltage. Powers RTC and

ACPI when VBAT is greater than VSB (by at

least 0.5V), and some external signals (see

Table 7-3).

2.4

3.0

3.6

VIO

I/O buffer power supply. Powers most of

the external signals (see Table 7-3); certain

signals within this power plane are 5V

tolerant.

3.135

3.3

3.465

VCORE

Core processor and internal digital power supply. Powers internal digital logic, including internal frequency

multipliers.

233 MHz Core clock frequency.

1.71

1.8

1.89

266 MHz Core clock frequency.

1.9

2.0

2.1

300 MHz Core clock frequency.

TBD

VPLL

PLL. Internal Phase Locked Loop (PLL)

power supply.

3.135

3.3

3.465

VSB

Standby power supply. Powers RTC and

ACPI when VSB is greater than VBAT -0.5V,

and some external signals (see Table 7-3).

3.135

3.3

3.465

VSBL

Standby logic. Powers internal logic needed to support Standby VSB.

VSBL (ball AD16) requires a 0.1 µF bypass capacitor to VSS.

233 MHz Core clock frequency.

1.71

1.8

1.89

266 MHz Core clock frequency.

1.9

2.0

2.1

300 MHz Core clock frequency.

TBD

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