SC1100 datasheet(293/348 Pages) NSC

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Electrical Specifications (Continued)

Table 7-9. SDRAM Interface Signals

Symbol

Parameter

Min

Max

Unit

Control Output1,2 Valid from SDCLK[3:0]

Control output includes all the following signals: RASA#, CASA#, WEA#, CKEA, DQM[7:0], and CS[1:0]#.

Load = 50 pF, VCORE = 1.8V - 2.1V, VIO = 3.3V, @25oC.

Use the Min/Max equations [value+(x * y)] to calculate the actual value.

x is the shift value which is applied to the SHFTSDCLK field, and y is 0.5 the core clock period.

Note that the SHFTSDCLK field = GX_BASE+8404h[5:3]. See the GX1 Processor Series datasheet.

For example, for a 233 MHz SC1100 processor running a 78 MHz SDRAM clock, with a shift value of 3:

t1 Min = -3.0 + (3 * (4.29 * 0.5)) = 3.435 ns

t1 Max = 0.1 + (3 * (4.29 * 0.5)) = 6.535 ns

-3.9 + (x*y)

0.1 + (x*y)

MA[12:0], BA[1.0] Output2 Valid from SDCLK[3:0]

-3.9 + (x*y)

0.1 + (x*y)

MD[63.0] Output2 Valid from SDCLK[3:0]

-3.9 + (x*y)

0.7 + (x*y)

MD[63:0] Read Data in Setup to SDCLK_IN

1.3

MD[63:0] Read Data Hold to SDCLK_IN

2.0

SDCLK[3:0], SDCLK_OUT cycle time

233 MHz / 3.0

10.0

14.0

266 MHz / 3.0

8.3

13.5

300 MHz / 3.0

7.3

12.5

SDCLK, SDCLK_OUT fall/rise time between (VOLD-VOHD)1

SDCLK[3:0], SDCLK_OUT high time

233 MHz / 3.0

4.0

266 MHz / 3.0

3.0

300 MHz / 3.0

2.5

SDCLK[3:0], SDCLK_OUT low time

233 MHz / 3.0

4.0

266 MHz / 3.0

2.5

300 MHz / 3.0

2.5

t10

SDCLK_IN fall/rise time between (VILD-VIHD)1

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