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SC1100 Datasheet(PDF) 152 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 152 Page - National Semiconductor (TI) |
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152 / 348 page  www.national.com 152 Revision 1.1 Core Logic Module (Continued) 5.3.2 Register Summary The tables in this subsection summarize the registers of the Core Logic module. Included in the tables are the register’s reset values and page references where the bit formats are found. Note: Function 4 (F4) is reserved. Table 5-14. F0: PCI Header and Bridge Configuration Registers for GPIO and LPC Support Summary F0 Index Width (Bits) Type Name Reset Value Reference (Table 5-29) 00h-01h 16 RO Vendor Identification Register 100Bh Page 166 02h-03h 16 RO Device Identification Register 0510h Page 166 04h-05h 16 R/W PCI Command Register 000Fh Page 166 06h-07h 16 R/W PCI Status Register 0280h Page 167 08h 8 RO Device Revision ID Register 00h Page 167 09h-0Bh 24 RO PCI Class Code Register 060100h Page 167 0Ch 8 R/W PCI Cache Line Size Register 00h Page 168 0Dh 8 R/W PCI Latency Timer Register 00h Page 168 0Eh 8 RO PCI Header Type Register 80h Page 168 0Fh 8 RO PCI BIST Register 00h Page 168 10h-13h 32 R/W Base Address Register 0 (F0BAR0) — Sets the base address for the I/O mapped GPIO Runtime and Configuration Registers (sum- marized in Table 5-15). 00000001h Page 168 14h-17h 32 R/W Base Address Register 1 (F0BAR1) — Sets the base address for the I/O mapped LPC Configuration Registers (summarized in Table 5-16) 00000001h Page 168 18h-2Bh -- -- Reserved 00h Page 168 2Ch-2Dh 16 RO Subsystem Vendor ID 100Bh Page 168 2Eh-2Fh 16 RO Subsystem ID 0500h Page 168 30h-3Fh -- -- Reserved 00h Page 168 40h 8 R/W PCI Function Control Register 1 39h Page 169 41h 8 R/W PCI Function Control Register 2 00h Page 169 42h -- -- Reserved 00h Page 169 43h 8 R/W PIT Delayed Transactions Register 02h Page 170 44h 8 R/W Reset Control Register 01h Page 170 45h -- -- Reserved 00h Page 170 46h 8 R/W PCI Functions Enable Register FEh Page 171 47h 8 R/W Miscellaneous Enable Register 00h Page 171 48h-4Bh -- -- Reserved 00h Page 171 4Ch-4Fh 32 R/W Top of System Memory FFFFFFFFh Page 171 50h 8 R/W PIT Control/ISA CLK Divider 7Bh Page 171 51h 8 R/W ISA I/O Recovery Control Register 40h Page 172 52h 8 R/W ROM/AT Logic Control Register 98h Page 172 53h 8 R/W Alternate CPU Support Register 00h Page 173 54h-59h -- -- Reserved 00h Page 173 5Ah 8 R/W Decode Control Register 1 01h Page 173 5Bh 8 R/W Decode Control Register 2 20h Page 174 5Ch 8 R/W PCI Interrupt Steering Register 1 00h Page 174 5Dh 8 R/W PCI Interrupt Steering Register 2 00h Page 175 5Eh-5Fh -- -- Reserved 00h Page 175 60h-63h 32 R/W ACPI Control Register 00000000h Page 175 64h-6Dh -- -- Reserved 00h Page 175 6Eh-6Fh 16 R/W ROM Mask Register FFF0h Page 176 |
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