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Revision 1.1

Core Logic Module (Continued)

5.2.13.1 LPC Interface Signal Definitions

The LPC specification lists seven required and six optional

signals for supporting the LPC interface. Many of the sig-

nals are the same signals found on the PCI interface and

do not require any new pins on the host. Required signals

must be implemented by both hosts and peripherals.

Optional signals may or may not be present on particular

hosts or peripherals.

The Core Logic module incorporates all the required LPC

interface signals and two of the optional signals:

• Required LPC signals:

— LAD[3:0] - Multiplexed Command, Address and Data.

— LFRAME# - Frame: Indicates start of a new cycle,

termination of broken cycle.

— LRESET# - Reset: This signal is not available. Use

PCI Reset signal PCIRST# instead.

— LCLK - Clock: This signal is not available. Use PCI

33 MHz clock signal PCICLK (ball AA23) instead.

• Core Logic module optional LPC signals:

— LDRQ# - Encoded DMA/Bus Master Request: Only

needed by peripheral that need DMA or bus

mastering. Peripherals may not share the LDRQ#

signal.

— SERIRQ - Serialized IRQ: Only needed by periph-

erals that need interrupt support.

5.2.13.2 Cycle Types

Table 5-12 shows the various types of cycles that are sup-

ported by the Core Logic module.

5.2.13.3 LPC Interface Support

The LPC interface supports all the features described in

the LPC Bus Interface specification, revision 1.0, with the

following exceptions:

• Only 8- or 16-bit DMA, depending on channel number.

Does not support the optional larger transfer sizes.

• Only one external DRQ pin.

Table 5-12. Cycle Types

Cycle Type

Supported Sizes

(Bytes)

Memory Read

Memory Write

I/O Read

I/O Write

DMA Read

1 or 2

DMA Write

1 or 2

Bus Master Memory Read

1, 2, or 4

Bus Master Memory Write

1, 2, or 4

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