SC1100 datasheet(146/348 Pages) NSC

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Revision 1.1

Core Logic Module (Continued)

5.2.12.2 AC97 Codec Interface

The AC97 codec (e.g., LM4548) is the master of the serial

interface and generates the clocks to Core Logic module.

Figure 5-13 shows the signal connections between a codec

and the SC1100:

For PC speaker synthesis, the Core Logic module outputs

the PC speaker signal on the PC_BEEP ball which is con-

nected to the PC_BEEP input of the AC97 codec. Note that

PC_BEEP is muxed on ball AE18 with GPIO16+IRRX1

and must be programmed via PMR[0] (see Table 3-2 on

page 50).

Codec Configuration/Control Registers

The codec 32-bit related registers:

• Codec GPIO Status Register

(F3BAR0+Memory Offset 00h)

• Codec GPIO Control Register

(F3BAR0+Memory Offset 04h)

• Codec Status Register

(F3BAR0+Memory Offset 08h)

• Codec Command Register

(F3BAR0+Memory Offset 0Ch)

Codec GPIO Status and Control Registers:

The Codec GPIO Status and Control registers are used for

codec GPIO related tasks such as enabling a codec GPIO

interrupt to cause an SMI.

Codec Status Register:

The Codec Status register stores the codec status WORD.

It is updated every valid Status Word slot.

Codec Command Register:

The Codec Command register writes the control WORD to

the codec. By writing the appropriate control WORDs to

this port, the features of the codec can be controlled. The

contents of this register are written to the codec during the

Control Word slot.

The bit formats for these registers are given in Table 5-38

"F3BAR0+Memory Offset: XpressAUDIO Configuration

Registers" on page 232.

Figure 5-13. AC97 V2.0 Codec Signal Connections

BIT_CLK

PC_BEEP

SDATA_OUT

AC97_CLK

PC_BEEP

SDATA_OUT

SDATA_IN

Codec

BIT_CLK

XTAL_I

SYNC

SDATA_IN

Geode™

SC1100

SC1100 Datasheet(PDF) 146 Page - National Semiconductor (TI)

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