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SC1100 Datasheet(PDF) 158 Page - National Semiconductor (TI) |
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SC1100 Datasheet(HTML) 158 Page - National Semiconductor (TI) |
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158 / 348 page  www.national.com 158 Revision 1.1 Core Logic Module (Continued) Table 5-20. F2: PCI Header Registers for IDE Controller Support Summary F2 Index Width (Bits) Type Name Reset Value Reference (Table 5-35) 00h-01h 16 RO Vendor Identification Register 100Bh Page 225 02h-03h 16 RO Device Identification Register 0502h Page 225 04h-05h 16 R/W PCI Command Register 0000h Page 225 06h-07h 16 RO PCI Status Register 0280h Page 225 08h 8 RO Device Revision ID Register 01h Page 225 09h-0Bh 24 RO PCI Class Code Register 010180h Page 225 0Ch 8 RO PCI Cache Line Size Register 00h Page 225 0Dh 8 RO PCI Latency Timer Register 00h Page 225 0Eh 8 RO PCI Header Type Register 00h Page 225 0Fh 8 RO PCI BIST Register 00h Page 225 10h-13h 32 RO Base Address Register 0 (F2BAR0) — Reserved for possible future use by the Core Logic module. 00000000h Page 225 14h-17h 32 RO Base Address Register 1 (F2BAR1) — Reserved for possible future use by the Core Logic module. 00000000h Page 225 18h-1Bh 32 RO Base Address Register 2 (F2BAR2) — Reserved for possible future use by the Core Logic module. 00000000h Page 225 1Ch-1Fh 32 RO Base Address Register 3 (F2BAR3) — Reserved for possible future use by the Core Logic module. 00000000h Page 225 20h-23h 32 R/W Base Address Register 4 (F2BAR4) — Sets the base address for the I/O mapped Bus Master IDE Registers (summarized in Table 5-21) 00000001h Page 225 24h-2Bh -- -- Reserved 00h Page 225 2Ch-2Dh 16 RO Subsystem Vendor ID 100Bh Page 225 2Eh-2Fh 16 RO Subsystem ID 0502h Page 225 30h-3Fh -- -- Reserved 00h Page 225 40h-43h 32 R/W Channel 0 Drive 0 PIO Register 00009172h Page 226 44h-47h 32 R/W Channel 0 Drive 0 DMA Control Register 00077771h Page 227 48h-4Bh 32 R/W Channel 0 Drive 1 PIO Register 00009172h Page 227 4Ch-4Fh 32 R/W Channel 0 Drive 1 DMA Control Register 00077771h Page 227 50h-FFh -- -- Reserved 00h Page 228 Table 5-21. F2BAR4: IDE Controller Support Registers Summary F2BAR4+ I/O Offset Width (Bits) Type Name Reset Value Reference (Table 5-36) 00h 8 R/W IDE Bus Master 0 Command Register — Primary 00h Page 229 01h -- -- Not Used -- Page 229 02h 8 R/W IDE Bus Master 0 Status Register — Primary 00h Page 229 03h -- -- Not Used -- Page 229 04h-07h 32 R/W IDE Bus Master 0 PRD Table Address — Primary 00000000h Page 229 |
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