DS26521 datasheet(133/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

133 of 258

RCR3

Receive Control Register 3

083h

Bit #

Name

—

RSERC

—

PLB

FLB

Default

Bit 5: RSER Control (RSERC).

0 = allow RSER to output data as received under all conditions (normal operation)

1 = force RSER to one under loss of frame alignment conditions

Bit 1: Payload Loopback (PLB).

0 = loopback disabled

1 = loopback enabled

When PLB is enabled, the following will occur:

1) Data will be transmitted from the TTIP and TRING pins synchronous with RCLK instead of TCLK.

2) All the receive-side signals will continue to operate normally.

3) The TCHCLK and TCHBLK signals are forced low.

4) Data at the TSER, TDATA, and TSIG pins is ignored.

5) The TLCLK signal will become synchronous with RCLK instead of TCLK.

In a PLB situation, the DS26521 loops the 192 bits (248 for E1) of payload data (with BPVs corrected) from the

receive section back to the transmit section. The transmitter follows the frame alignment provided by the receiver.

The receive frame boundary is automatically fed into the transmit section, such that the transmit frame position is

locked to the receiver (i.e., TSYNC is sourced from RSYNC). The FPS framing pattern, CRC-6 calculation, and the

FDL bits (FAS word, Si, Sa, E bits, and CRC-4 for E1) are not looped back. Rather, they are reinserted by the

DS26521 (i.e., the transmit section will modify the payload as if it was input at TSER).

Bit 0: Framer Loopback (FLB).

0 = loopback disabled

1 = loopback enabled

This loopback is useful in testing and debugging applications. In FLB, the DS26521 loops data from the transmit

side back to the receive side. When FLB is enabled, the following will occur:

1) (T1 mode) An unframed all-ones code will be transmitted at TTIP and TRING.

(E1 mode) Normal data will be transmitted at TTIP and TRING.

2) Data at RTIP and RRING will be ignored.

3) All receive-side signals will take on timing synchronous with TCLK instead of RCLK.

4) Note that it is not acceptable to have RCLK tied to TCLK during this loopback because this will cause an

unstable condition.

DS26521 Datasheet(PDF) 133 Page - Maxim Integrated Products

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