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DS26521 Datasheet(PDF) 187 Page - Maxim Integrated Products |
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DS26521 Datasheet(HTML) 187 Page - Maxim Integrated Products |
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187 / 258 page ![]() DS26521 Single T1/E1/J1 Transceiver 187 of 258 Register Name: TESCR Register Description: Transmit Elastic Store Control Register Register Address: 185h Bit # 7 6 5 4 3 2 1 0 Name TDATFMT TGCLKEN — TSZS TESALGN TESR TESMDM TESE Default 0 0 0 0 0 0 0 0 Note: Bits 7 and 6 are used for fractional backplane support. See Section 8.8.5. Bit 7: Transmit Channel Data Format (TDATFMT). 0 = 64kbps (data contained in all 8 bits) 1 = 56kbps (data contained in 7 out of the 8 bits) Bit 6: Transmit Gapped-Clock Enable (TGCLKEN). 0 = TCHCLK functions normally 1 = enable gapped bit clock output on TCHCLK Bit 4: Transmit Slip Zone Select (TSZS). This bit determines the minimum distance allowed between the elastic store read and write pointers before forcing a controlled slip. This bit is only applies during T1-to-E1 or E1-to-T1 conversion applications. 0 = force a slip at 9 bytes or less of separation (used for clustered blank channels) 1 = force a slip at 2 bytes or less of separation (used for distributed blank channels) Bit 3: Transmit Elastic Store Align (TESALGN). Setting this bit from 0 to 1 will force the transmit elastic store’s write/read pointers to a minimum separation of half a frame. No action will be taken if the pointer separation is already greater or equal to half a frame. If pointer separation is less than half a frame, the command will be executed and the data will be disrupted. Should be toggled after TSYSCLK has been applied and is stable. Must be cleared and set again for a subsequent align. Bit 2: Transmit Elastic Store Reset (TESR). Setting this bit from 0 to 1 will force the read pointer into the same frame that the write pointer is exiting, minimizing the delay through the elastic store. If this command should place the pointers within the slip zone (see bit 4), then an immediate slip will occur and the pointers will move back to opposite frames. Should be toggled after TSYSCLK has been applied and is stable. Do not leave this bit set HIGH. Bit 1: Transmit Elastic Store Minimum-Delay Mode (TESMDM). 0 = elastic stores operate at full two-frame depth 1 = elastic stores operate at 32-bit depth Bit 0: Transmit Elastic Store Enable (TESE). 0 = elastic store is bypassed 1 = elastic store is enabled |
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