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Integrated Functions (Continued)

4.5.7.3

VGA Display Support

The graphics pipeline contains full hardware support for the

VGA front end. The VGA data is stored in a 256 KB buffer

located in graphics memory. The main task for Virtual VGA

(see Section 4.6 “Virtual VGA Subsystem” on page 158) is

converting the data in the VGA buffer to an 8-bpp frame

buffer that can be displayed by the display controller.

For some modes, the display controller can display the

VGA data directly and the data conversion is not neces-

sary. This includes standard VGA mode 13h and the varia-

tions of that mode used in several games; the display

controller can also directly display VGA planar graphics

modes D, E, F, 10, 11, and 12. Likewise, the hardware can

directly display all of the higher-resolution VESA modes.

Since the frame buffer data is written directly to memory

instead of travelling across an external bus, the GX1 pro-

cessor often outperforms VGA cards for these modes.

The display controller, however, does not directly support

text modes. SoftVGA must convert the characters and

attributes in the VGA buffer to an 8-bpp frame buffer image

the hardware uses for display refresh.

4.5.8

Display Controller Registers

The Display Controller maps 100h memory locations start-

ing at GX_BASE+8300h for the display controller registers.

Refer to Section 4.1.2 “Control Registers” on page 99 for

instructions on accessing these registers.

The display controller registers are divided into six catego-

ries:

• Configuration and Status registers

• Memory Organization registers

• Timing registers

• Cursor and Line Compare registers

• Color registers

• Palette and RAM Diagnostic registers

Table 4-28 summarizes these registers and locations, and

the following subsections give detailed register/bit formats.

Table 4-28. Display Controller Register Summary

GX_BASE+

Memory

Offset

Type

Name/Function

Default

Value

Configuration and Status Registers

8300h-8303h

R/W

DC_UNLOCK

Display Controller Unlock: This register is provided to lock the most critical memory-

mapped display controller registers to prevent unwanted modification (write operations).

Read operations are always allowed.

00000000h

8304h-8307h

R/W

DC_GENERAL_CFG

Display Controller General Configuration: General control bits for the display controller.

00000000h

8308h-830Bh

R/W

DC_TIMING_CFG

Display Controller Timing Configuration: Status and control bits for various display

timing functions.

xx000000h

830Ch-830Fh

R/W

DC_OUTPUT_CFG

Display Controller Output Configuration: Status and control bits for pixel output

formatting functions.

xx000000h

Memory Organization Registers

8310h-8313h

R/W

DC_FB_ST_OFFSET

Display Controller Frame Buffer Start Address: Specifies offset at which the frame buffer

starts.

xxxxxxxxh

8314h-8317h

R/W

DC_CB_ST_OFFSET

Display Controller Compression Buffer Start Address: Specifies offset at which the com-

pressed display buffer starts.

xxxxxxxxh

8318h-831Bh

R/W

DC_CUR_ST_OFFSET

Display Controller Cursor Buffer Start Address: Specifies offset at which the cursor memory

buffer starts.

xxxxxxxxh

831Ch-831Fh

Reserved

00000000h

8320h-8323h

R/W

DC_VID_ST_OFFSET

Display Controller Video Start Address: Specifies offset at which the video buffer starts.

xxxxxxxxh

8324h-8327h

R/W

DC_LINE_DELTA

Display Controller Line Delta: Stores line delta for the graphics display buffers.

xxxxxxxxh

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