GX1 datasheet(145/247 Pages) NSC

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Integrated Functions (Continued)

11:8

DFIFO

HI-PRI

START LVL

Display FIFO High Priority Start Level: This field specifies the depth of the display FIFO (in 64-bit entries

x 4) at which a high-priority request will be sent to the memory controller to fill up the FIFO. The value is

dependent upon display mode.

This register should always be nonzero and should be less than the high-priority end level.

7:6

DCLK_

DIV

DCLK Divider: This 2-bit field specifies the clock divider for the input DCLK pin.

00 = Forced Low

01 = DCLK ÷ 2

10 = DCLK

11 = DCLK

5DECE

Decompression Enable: Allow operation of internal decompression hardware:

0 = Disable; 1 = Enable.

4CMPE

Compression Enable: Allow operation of internal compression hardware: 0 = Disable; 1 = Enable

3PPC

Pixel Panning Compatibility: This bit has the same function as that found in the VGA.

Allow pixel alignment to change when crossing a split-screen boundary - it will force the pixel alignment to

be 16-byte aligned: 0 = Disable; 1 = Enable.

If disabled, the previous alignment will be preserved when crossing a split-screen boundary.

2DVCK

Divide Video Clock: Selects frequency of VID_CLK pin:

0 = VID_CLK pin frequency is equal to one-half (½) the frequency of the core clock.

1 = VID_CLK pin frequency is equal to one-fourth (¼) the frequency of the core clock.

Bit 28 (VIDE) must be set to 1 for this bit to be valid.

1CURE

Cursor Enable: Use internal hardware cursor: 0 = Disable; 1 = Enable.

0DFLE

Display FIFO Load Enable: Allow the display FIFO to be loaded from memory:

0 = Disable; 1 = Enable.

If disabled, no write or read operations will occur to the display FIFO.

If enabled, a flat panel should be powered down prior to setting this bit low. Similarly, if active, a CRT should

be blanked prior to setting this bit low.

GX_BASE+8308h-830Bh

DC_TIMING_CFG Register (R/W) (Locked)

Default Value = xxx00000h

VINT

(RO)

Vertical Interrupt (Read Only): Is a vertical interrupt pending? 0 = No; 1 = Yes.

This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3C2h bit 7.

VNA

(RO)

Vertical Not Active (Read Only): Is the active part of a vertical scan is in progress (i.e., retrace, blanking,

or border)? 0 = Yes; 1 = No.

This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3BA/3DA

bit 3.

DNA

(RO)

Display Not Active (Read Only): Is the active part of a line is being displayed (i.e., retrace, blanking, or

border)? 0 = Yes; 1 = No.

This bit is provided to maintain backward compatibility with the VGA. It corresponds to VGA port 3BA/3DA

bit 0.

RSVD

Reserved: Set to 0.

DDCI

(RO)

DDC Input (Read Only): This bit returns the value from the DDCIN pin that should reflect the value from

pin 12 of the VGA connector. It is used to provide support for the VESA Display Data Channel standard

level DDC1.

26:20

RSVD

Reserved: Set to 0.

19:17

RSVD

Reserved: Set to 0.

BKRT

Blink Rate:

0 = Cursor blinks on every 16 frames for a duration of 8 frames (approximately 4 times per second) and

VGA text characters will blink on every 32 frames for a duration of 16 frames (approximately 2 times per

second).

1 = Cursor blinks on every 32 frames for a duration of 16 frames (approximately 2 times per second) and

VGA text characters blink on every 64 frames for a duration of 32 frames (approximately 1 time per sec-

ond).

Blinking is enabled by BLNK bit 7.

Table 4-29. Display Controller Configuration and Status Registers (Continued)

Bit

Name

Description

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