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GX1 Datasheet(PDF) 149 Page - National Semiconductor (TI) |
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GX1 Datasheet(HTML) 149 Page - National Semiconductor (TI) |
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149 / 247 page ![]() Revision 1.0 149 www.national.com Integrated Functions (Continued) GX_BASE+8324h-8327h DC_LINE_DELTA Register (R/W) (Locked) Default Value = xxxxxxxxh 31:22 RSVD Reserved: Set to 0. 21:12 CB_LINE_ DELTA Compressed Display Buffer Line Delta: This value represents number of DWORDs that, when added to the starting offset of the previous line, will point to the start of the next compressed line in memory. It is used to always maintain a pointer to the starting offset for the compressed display buffer line being loaded into the display FIFO. 11:10 RSVD Reserved: Set to 0. 9:0 FB_LINE_ DELTA Frame Buffer Line Delta: This value represents number of DWORDs that, when added to the starting offset of the previous line, will point to the start of the next frame buffer line in memory. It is used to always maintain a pointer to the starting offset for the frame buffer line being loaded into the display FIFO. GX_BASE+8328h-832Bh DC_BUF_SIZE Register (R/W) (Locked) Default Value = xxxxxxxxh 31:30 RSVD Reserved: Set to 0. 29:16 VID_BUF_ SIZE Video Buffer Size: These bits set the video buffer size, in 64-byte segments. The maximum size is 1 MB. 15:9 CB_LINE_ SIZE Compressed Display Buffer Line Size: This value represents the number of DWORDs for a valid compressed line plus 1. It is used to detect an overflow of the compressed data FIFO. It should never be larger than 41h since the maximum size of the compressed data FIFO is 64 DWORDs. 8:0 FB_LINE_ SIZE Frame Buffer Line Size: This value specifies the number of QWORD (8-byte segments) to transfer for each display line from the frame buffer. If panning is enabled, this value can generally be programmed to the displayed number of QWORD + 2 so that enough data is transferred to handle any possible alignment. Extra pixel data in the FIFO at the end of a line will automatically be discarded. GX_BASE+832Ch-832Fh Reserved Default Value = 00000000h Table 4-30. Display Controller Memory Organization Registers (Continued) Bit Name Description |
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