GX1 datasheet(152/247 Pages) NSC

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Integrated Functions (Continued)

GX_BASE+8348h-834Bh

DC_V_TIMING_3 Register (R/W) (Locked)

Default Value = xxxxxxxxh

31:27

RSVD

Reserved: Set to 0.

26:16

V_SYNC_END

Vertical Sync End: The line at which the CRT vertical sync signal becomes inactive minus 1.

15:11

RSVD

Reserved: Set to 0.

10:0

V_SYNC_START

Vertical Sync Start: The line at which the CRT vertical sync signal becomes active minus 1. For

interlaced display, note that the vertical counter is incremented twice during each line and since there

are an odd number of lines, the vertical sync pulse will trigger in the middle of a line for one field and

at the end of a line for the subsequent field.

Note:

These values are specified in lines.

GX_BASE+834Ch-834Fh

DC_FP_V_TIMING Register (R/W) (Locked)

Default Value = xxxxxxxxh

31:27

RSVD

Reserved: Set to 0.

26:16

FP_V_SYNC

_END

Flat Panel Vertical Sync End: The line at which the flat panel vertical sync signal becomes inactive

minus 2. Note that the internal flat panel vertical sync is latched by the flat panel horizontal sync prior

to being output to the panel.

15:11

RSVD

Reserved: Set to 0.

10:0

FP_VSYNC

_START

Flat Panel Vertical Sync Start: The line at which the internal flat panel vertical sync signal becomes

active minus 2. Note that the internal flat panel vertical sync is latched by the flat panel horizontal

sync prior to being output to the panel.

Note: These values are specified in lines.

Table 4-31. Display Controller Timing Registers (Continued)

Bit

Name

Description

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